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never stop thinking. hyb18t256321f?20 hyb18t256321f?22 hyb18t256321f?25 256-mbit gddr3 dram rohs compliant data sheet, rev. 1.52, june 2004 memory products
the information in this document is subject to change without notice. edition 06-2004 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hyb18t256321f?20 hyb18t256321f?22 hyb18t256321f?25 256-mbit gddr3 dram rohs compliant data sheet, rev. 1.52, june 2004 memory products
template: mp_a4_v2.3_2004-01-14.fm hyb18t256321f?20 hyb18t256321f?22 hyb18t256321f?25 revision history: rev. 1.52 06-2004 previous revision: rev. 1.5 2004-05 page subjects (major changes since last revision) 11 table 1: added cl7 22 added to note 2 and 3: exept for read, read/a. write, write/a ends t wtr after the first pos. edge of clk following the last falling wdqs edge. 37, 78 changed trcmin-2.0 to 37.2ns 50 table 25: deleted tdqsq min 69-76 changed t a <85 c to t c <85 c 70 table 34: v ih low changed we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
hyb18t256321f?[20/22/25] ddr sgram data sheet 5 rev. 1.52, 06-2004 05142004-zttv-e1oq 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 ball definition and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.1 command table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.2 description of commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 state diagram and truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.1 state diagram for one activated bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.2 function truth table for more than one activated bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.3 function truth table for cke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 clocks, cke, commands and addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3 programmable impedance output drivers and active terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.1 gddr3 io driver and termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.2 self calibration for driver and termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.3 dynamic switching of dq terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.4 output impedance and termination dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4 extended mode register set command (emrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.1 dll enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.2 wr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.3 termination rtt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.4 output driver impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.5 low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.6 vendor code and revision identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.5 mode register set command (mrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5.1 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.2 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.3 cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.5.4 write latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.5.5 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.5.6 dll reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.6 bank / row activation (act) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.7 writes (wr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.7.1 write basic information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.7.2 write - basic sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.7.3 write - consecutive bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.7.3.1 gapless bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.7.3.2 bursts with gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.7.4 write with autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.7.5 write followed by read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.7.6 write followed by dterdis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.7.7 write with autoprecharge followed by read / read with autoprecharge . . . . . . . . . . . . . . . . . . . . 47 3.7.8 write followed by precharge on same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.8 reads (rd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.8.1 read - basic information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.8.2 read - basic sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.8.3 consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.8.3.1 gapless bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table of contents
hyb18t256321f?[20/22/25] ddr sgram data sheet 6 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.8.5 read followed by write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.8.6 read followed by precharge on the same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.9 data termination disable (dterdis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.9.1 dterdis followed by read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.9.2 dterdis followed by write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.10 precharge (pre/preall) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.11 auto refresh command (aref) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.12 self-refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.12.1 self-refresh entry (srefen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.12.2 self-refresh exit (srefex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.13 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.2 recommended power & dc operation conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3 dc & ac logic input levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.4 differential clock dc and ac levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.5 output test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.6 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.7 driver current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.7.1 driver iv characteristics at 40 ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.8 termination iv characteristic at 60 ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.9 termination iv characteristic at 120 ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.10 termination iv characteristic at 240 ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.11 operating currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.11.1 operating current ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.12 operating current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.13 summary of timing parameters for ?2.0 ns, ?2.2 ns and ?2.5 ns speed sorts in dll on mode . . . . . 78 4.14 ac characteristics and settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.1 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
hyb18t256321f?[20/22/25] ddr sgram data sheet 7 rev. 1.52, 06-2004 05142004-zttv-e1oq table 1 key timing and power supply parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3 ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4 command overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5 description of commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6 minimum delay from rd/a and wr/a to any other command (to another bank) with concurrent autoprecharge 20 table 7 function truth table i. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8 function truth table ii (cke table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9 general timing parameters for -2.0 ns, -2.2 ns and -2.5 ns speed sorts. . . . . . . . . . . . . . . . . . . . 24 table 10 reset timing parameters for -2.0, -2.2 and -2.5 speed sorts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11 range of external resistance zq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12 termination types and activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13 termination update keep out time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 14 number of legs used for terminator and driver self calibration. . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 16 emrs timing parameters for ?2.0, ?2.2 and ?2.5 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 17 revision id and vendor code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 18 vendor code and revision id timing parameters for -2.0, -2.2 and -2.5 speed sorts . . . . . . . . . 32 table 19 mrs timing parameters for ?2.0, ?2.2 and ?2.5 speed sorts. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 20 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 21 act timing parameters for ?2.0, ?2.2 and ?2.5 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 22 mapping of wdqs and dm signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 23 wr timing parameters for ?2.0, ?2.2 and ?2.5 speed sorts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 24 wl / cl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 25 read timing parameters for -2.0 ns, -2.2 ns and -2.5 ns speed sorts . . . . . . . . . . . . . . . . . . . . . 50 table 26 ba1, ba0 precharge bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 27 precharge timing parameters for ?2.0, ?2.2 and ?2.5 speed sorts . . . . . . . . . . . . . . . . . . . . . . . 63 table 28 autorefresh timing parameters for ?2.0, ?2.2 and ?2.5 speed sorts . . . . . . . . . . . . . . . . . . . . . . 64 table 29 self refresh exit timing parameter for ?2.0, ?2.2 and ?2.5 speed sorts . . . . . . . . . . . . . . . . . . . 66 table 30 power down exit timing parameter for ?2.0, ?2.2 and ?2.5 speed sorts . . . . . . . . . . . . . . . . . . . 67 table 31 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 32 operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 33 power & dc operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 34 dc & ac logic input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 35 differential clock dc and ac input conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 36 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 37 programmed driver iv characteristics at 40 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 38 programmed terminator characterisitc at 60 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 table 39 programmed terminator characterisitics at 120 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 40 programmed terminator characterisitc at 240 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 41 operating current ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 42 operating current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 43 timing parameters for ?2.0, ?2.2 and ?2.5 speed sorts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 44 hyb18t256321f?20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 45 hyb18t256321f?22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 46 hyb18t256321f?25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 47 p-fbga 144 package thermal resitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
hyb18t256321f?[20/22/25] ddr sgram data sheet 8 rev. 1.52, 06-2004 05142004-zttv-e1oq
hyb18t256321f?[20/22/25] ddr sgram data sheet 9 rev. 1.52, 06-2004 05142004-zttv-e1oq figure 1 standard ballout 256 mbit gddr3 graphics ram [500mhz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3 state diagram for one bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 4 clock, cke and command/address timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5 power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 6 output driver simplified schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7 termination update keep out time after autorefresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8 self calibration of pmos and nmos legs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 9 odt disable timing during a read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 figure 10 extended mode register bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 11 extended mode register bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12 extended mode register set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 13 timing of vendor code and revision id generation on dq[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 14 mode register set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 15 mode register bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 16 mode register set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 17 activating a specific row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 18 bank activation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 19 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 20 basic write burst / dm timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 21 write burst basic sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 22 gapless write bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 23 consecutive write bursts with gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 24 write with autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 25 write followed by read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 26 write command followed by dterdis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 27 write with autoprecharge followed by read or read with autoprecharge on another bank . . . . . 47 figure 28 write followed by precharge on same bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 29 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 30 basic read burst timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 31 read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 32 gapless consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 33 consecutive read bursts with gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 34 read command followed by dterdis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 35 read with autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 36 read followed by write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 37 read followed by precharge on the same bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 38 data termination disable command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 39 dternis timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 40 dternis followed by dternis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 41 dterdis command followed by read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 42 dterdis command followed by write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 43 precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 44 precharge timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 45 auto refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 46 auto refresh cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 47 self refresh entry command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 48 self refresh entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 49 self refresh exit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 50 self refresh exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 51 power down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 52 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 53 output test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 54 40 ohm driver pull-down and pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 55 60 ohm active termination characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
hyb18t256321f?[20/22/25] ddr sgram data sheet 10 rev. 1.52, 06-2004 05142004-zttv-e1oq figure 56 120 ohm active termination characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 57 240 ohm active termination characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 58 package outline fbga. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
256-mbit gddr3 dram hyb18t256321f?20 hyb18t256321f?22 hyb18t256321f?25 data sheet 11 rev. 1.52, 06-2004 05142004-zttv-e1oq 1 overview 1.1 features maximum clock frequency of 500 mhz organization: 2048k x 32 x 4 banks 4096 rows and 512 columns (128 burst start locations) per bank differential clock inputs (clk and clk ) cas latencies of 5, 6 and 7 write latencies of 2, 3, 4 fixed burst sequence with length of 4. 4n prefetch short ras to cas timing for writes t ras lockout support t wr programmable for writes with auto-precharge data mask for write commands single ended read strobe (rdqs) per byte. rdqs edge-aligned with read data single ended write strobe (wdqs) per byte. wdqs center-aligned with write data dll aligns rdqs and dq transitions with clock programmable io interface including on chip termination (odt) autoprecharge option with concurrent autoprecharge support 4k refresh (32ms) autorefresh and self refresh p-tfbga 144 package (11mmx11mm) v dd / v ddq voltage (according to table 1 ) calibrated output drive. active termination support. rohs compliant 1) 1)rohs compliant product: restriction of the use of certain hazardous substances (rohs) in electrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. table 1 key timing and power supply parameters speed sort - 2.0 - 2.2 - 2.5 units power supply v dd / v ddq 2.0 100 mv 2.0 100 mv 2.0 100 mv v cas latency = 7 t ck7 min 2.0 2.2 2.5 ns f ck7 max 500 455 400 mhz cas latency = 6 t ck6 min 2.0 2.2 2.5 ns f ck6 max 500 455 400 mhz cas latency = 5 t ck5 min ?2.73.0ns f ck5 max ? 370 333 mhz access time t acmin ?0.4 ?0.45 ?0.5 ns t acmax 0.4 0.45 0.5 ns rdqs-dq skew t dqsq 0.225 0.25 0.28 ns
hyb18t256321f?[20/22/25] ddr sgram overview data sheet 12 rev. 1.52, 06-2004 05142004-zttv-e1oq 1.2 general description the infineon 256 mbit gddr3 graphics ram [500mhz] is a high speed memory device, designed for high bandwidth intensive applications like pc graphics systems. the chip?s quad bank architecture is optimized for high speed and achieves a peak bandwidth of 4 gbyte/s using a 32 bit interface and a maximum system clock of 500 mhz. hyb18t256321f uses a double data rate interface and a 4 n -prefetch architecture. the gddr3 interface transfers two 32 bit wide data words per clock cycle to/from the i/o pins. corresponding to the 4 n -prefetch a single write or read access consists of a 128 bit wide, one-clock-cycle data transfer at the internal memory core and four corresponding 32 bit wide, one-half- clock-cycle data transfers at the i/o pins. single-ended unidirectional read and write data strobes are transmitted simultaneously with read and write data respectively in order to capture data properly at the receivers of both the graphics sdram and the controller. data strobes are organized per byte of the 32 bit wide interface. for read commands the rdqs are edge-aligned with data, and the wdqs are center- aligned with data for write commands. the hyb18t256321f operates from a differential clock (clk and clk ). commands (addresses and control signals) are registered at every positive edge of clk. input data is registered on both edges of wdqs, and output data is referenced to both edges of rdqs. in this document references to ?the positive edge of clk? imply the crossing of the positive edge of clk and the negative edge of clk . similarly, the ?negative edge of clk? refers to the crossing of the negative edge of clk and the positive edge of clk . references to rdqs are to be interpreted as any or all rdqs<3:0>. wdqs, dm and dq should be interpreted in a similar fashion. read and write accesses to the hyb18t256321f are burst oriented. the burst length is fixed to 4 and the two least significant bits of the burst address are ?don?t care? and internally set to low. accesses begin with the registration of an activate command, which is then followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and the row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the column location for the burst access. each of the 4 banks consists of 4096 row locations and 512 column locations. an auto precharge function can be combined with read and write to provide a self-timed row precharge that is initiated at the end of the burst access. the pipelined, multibank architecture of the hyb18t256321f allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. the device is supplied with 2.0 v for output drivers and core. ( v dd / v ddq voltages see table 1 ) the ?on die termination? interface (odt) is optimized for high frequency digital data transfers and is internally controlled. the termination resistor value can be set using an external zq resistor or disabled through the extended mode register. the output driver impedance can be set using the extended mode register. it can either be set to zq / 6 (autocalibration) or to 35, 40 or 45 ohms. auto refresh and power down with self refresh operations are supported. a standard jedec p-tfbga 144 package is used which enables ultra high speed data transfer rates and a simple upgrade path from former ddr graphics sdram products. table 2 ordering information part number 1) 1) hyb: designator for memory components 256: 256-mbit density f: lead free organisation v dd / v ddq (v) clock (mhz) package hyb18t256321f?20 32 2.0 500 p-tbga 144 hyb18t256321f?22 2.0 455 hyb18t256321f?25 2.0 400
hyb18t256321f?[20/22/25] ddr sgram pin configuration data sheet 13 rev. 1.52, 06-2004 05142004-zttv-e1oq 2 pin configuration figure 1 standard ballout 256 mbit gddr3 graphics ram [500mhz] note: figure shows top view 144 ball p-tfbga: top view 123 12 10 11 d b c h e f g m j k l v ssq a v ssq 9 78 6 45 dq 4 wdqs 0 dq 3 dm 0 v ddq dq 2 dq 0 dq 31 dq 29 dq 28 dm 3 wdqs 3 v ddq dq 1 v ddq v ddq dq 30 v ddq v ddq dq 26 dq 27 dq 6 dq 5 v ssq v ssq v ssq v dd v dd v ssq v ssq v ssq dq 24 dq 25 rfu v dd v ss v ssq v ss v ss v ssq v ss v dd dq 7 rfu dq 17 dq 16 v ddq v ssq v ssq dq 15 v ddq dq 14 dq 12 dq 13 dq 11 v ssq dq 8 v ssq dq 9 dm 1 wdqs 1 dq 10 v ref v ddq v ssq dq 18 dq 19 v ddq v ssq v ssq dq 20 dm 2 wdqs 2 dq 21 dq 22 v ddq v ssq dq 23 v ddq v ssq v ss v ss a 6 v ssq cke v ddq clk zq v dd a 5 a 9 v ss rfu a 10 v dd v dd a 2 v ss ras# we# v dd cas# cs# ba 1 ba 0 reset rfu a 1 a 3 a 0 a 11 a 4 rfu a 7 clk# a 8 /ap v ss v ss rdqs 0 rdqs 1 rdqs 2 rdqs 3 v ref v ss therm v ss therm v ss therm v ss therm v ss therm v ss therm v ss therm v ss therm v ss therm v ss therm v ss therm v ss therm v ss therm v ss therm v ss therm v ss therm v ddq v ddq v ddq
hyb18t256321f?[20/22/25] ddr sgram pin configuration data sheet 14 rev. 1.52, 06-2004 05142004-zttv-e1oq 2.1 ball definition and description table 3 ball description ball type detailed function clk, clk input clock: clk and clk are differential clock inputs. address and command inputs are latched on the positive edge of clk. graphics sdram outputs (rdqs, dqs) are referenced to clk. clk and clk are not internally terminated. cke input clock enable: cke high activates and cke low deactivates the internal clock and input buffers. taking cke low provides power down. if all banks are precharged, this mode is called precharge power down and self refresh mode is entered if a autorefresh command is issued. if at least one bank is open, active power down mode is entered and no self refresh allowed. all input receivers except clk, clk and cke are disabled during power down. in self refresh mode the clock receivers are disabled too. self refresh exit is performed by setting cke asynchronously high. exit of power down without self refresh is accomplished by setting cke high with a positive edge of clk. the value of cke is latched asynchronously by reset during power on to determine the value of the termination resistor of the address and command inputs. cke is not allowed to go low during a rd, a rw or a snoop burst. cs input chip select: cs enables the command decoder when low and disables it when high. when the command decoder is disabled, new commands with the exeption of deternis are ignored, but internal operations continue. cs is one of the four command balls. ras , cas , we input command inputs: sampled at the positive edge of clk, cas , ras , and we define (together with cs ) the command to be executed. dq<0:31> i/o data input/output: the dq signals form the 32 bit data bus. during reads the balls are outputs and during writes they are inputs. data is transferred at both edges of rdqs. dm<0:3> input input data mask: the dm signals are input mask signals for write data. data is masked when dm is sampled high with the write data. dm is sampled on both edges of wdqs. dm0 is for dq<0:7>, dm1 is for dq<8:15>, dm2 is for dq<16:23> and dm3 is for dq<24:31>. although dm balls are input-only, their loading is designed to match the dq and wdqs balls. rdqs<0:3> output read data strobes: rdqsx are unidirectional strobe signals. during reads the rdqsx are transmitted by the graphics sdram and edge-aligned with data. rdqs have preamble and postamble requirements. rdqs0 is for dq<0:7>, rdqs1 for dq<8:15>, rdqs2 for dq<16:23> and rdqs3 for dq<24:31>. wdqs<0:3> input write data strobes: wdqs are unidirectional strobe signals. during writes the wdqs are generated by the controller and center aligned with data. wdqs have preamble and postamble requirements. wdqs0 is for dq<0:7>, wdqs1 for dq<8:15>, wdqs2 for dq<16:23> and wdqs3 for dq<24:31>. ba<0:1> input bank address inputs: ba select to which internal bank an activate, read, write or precharge command is being applied. ba are also used to distinguish between the mode register set and extended mode register set commands. a<0:11> input address inputs: during activate, a0-a11 defines the row address. for read/write, a2-a7 and a9 defines the column address, and a8 defines the auto precharge bit. if a8 is high, the accessed bank is precharged after execution of the column access. if a8 is low, auto precharge is disabled and the bank remains active. sampled with precharge, a8 determines whether one bank is precharged (selected by ba<0:1>, a8 low) or all 4 banks are precharged (a8 high). during (extended) mode register set the address inputs define the register settings. a<0:11> are sampled with the positive edge of clk. zq - odt impedance reference: the zq ball is used to control the odt impedance.
hyb18t256321f?[20/22/25] ddr sgram pin configuration data sheet 15 rev. 1.52, 06-2004 05142004-zttv-e1oq res input reset pin: the res pin is a v ddq cmos input. res is not internally terminated. the low to high transition of the reset signal is used to latch the cke value during power on in order to set the value of the termination resistors of the address and command inputs. when res is low, all terminations are switched off. the low to high transition of the res signal must occur at the beginning of the power up sequence in order to insure functionnality. v ref supply voltage reference: v ref is the reference voltage input. v dd , v ss supply power supply: power and ground for the internal logic. v ddq , v ssq supply i/o power supply: isolated power and ground for the output buffers to provide improved noise immunity. nc, rfu - please do not connect no connect and reserved for future use balls. table 3 ball description ball type detailed function
hyb18t256321f?[20/22/25] ddr sgram pin configuration data sheet 16 rev. 1.52, 06-2004 05142004-zttv-e1oq 2.2 functional block diagram figure 2 functional block diagram column decoder sense amplifiers and data bus buffer memory array bank 0 4096 x 512 x 32 bit column decoder sense amplifiers and data bus buffer column decoder sense amplifiers and data bus buffer column decoder sense amplifiers and data bus buffer memory array 4096 x 512 x 32 bit memory array 4096 x 512 x 32 bit memory array 4096 x 512 x 32 bit bank 1 bank 2 bank 3 row decoder row decoder row decoder row decoder input buffers output buffers clk clk# cke dll dq24-dq31 data dm3 rdqs3 wdqs3 dq16-dq23 data dm2 rdqs2 wdqs2 dq8-dq15 data dm1 rdqs1 wdqs1 dq0-dq7 data dm0 rdqs0 wdqs0 row addresses a0-a11, ba0-ba1 row address buffer column address buffer column addresses a2-a7,a9 refresh counter control logic & timing generator address buffer a0-a7,a9, a8/ap, a10-a11 ba0, ba1 mode register a8/ap cs# ras# cas# we# zq res
hyb18t256321f?[20/22/25] ddr sgram pin configuration data sheet 17 rev. 1.52, 06-2004 05142004-zttv-e1oq 2.3 commands 2.3.1 command table in the following table cken refers to the positive edge of clk corresponding to the clock cycle when the command is given to the graphics sdram. cken-1 refers to the previous positive edge of clk. for all command and address inputs cken is implied. all input states or sequences not shown are illegal or reserved. 1. x represents ?don?t care?. 2. ba0 and ba1 provide bank address, a0 - a11 provide the row address. 3. ba0 and ba1 provide bank address, a2- a7, a9 provide the column address, a8/ap controls auto precharge. 4. auto refresh and self refresh entry differ only by the state of cke 5. pwdnen is selected by issuing a desel or nop at the first positive clk edge following the high to low transition of cke. 6. first possible valid command after t xpn . during t xpn only nop or desel commands are allowed. 7. self refresh is selected by issuing aref at the first positive clk edge following the high to low transition of cke. 8. first possible valid command after t xsc . during t xsc only nop or desel commands are allowed. 9. this command is invoked when a read is issued on another dram rank placed on the same command bus. cannot be in power-down or self-refresh state. the read command will cause the data termination to be disabled. refer to for timing. abbreviations: ba:bank address col.:column address table 4 command overview operation code cke n-1 cke n cs ras cas we ba0 ba1 a8 a2-7 a9-11 note device deselect desel h h h l x h x x h x l h xxxx 1 data terminator disable dterdis h h h h l h x x x x 1,9 no operation nop h h l h h h x x x x mode register set mrs h h l l l l 0 0 opcode extended mode register set emrs h h l l l l 1 0 opcode bank activate act h h l l h h ba ba row address 1,2 read rd h h l h l h ba ba l col. 1,3 read w/ autoprecharge rd/a h h l h l h ba ba h col. 1,3 write wr h h l h l l ba ba l col. 1,3 write w/ autoprecharge wr/a h h l h l l ba ba h col. 1,3 precharge pre h h l l h l ba ba l x 1 precharge all preall h h l l h l x x h x 1 auto refresh aref h h l l l h x x x x 1,4 power down mode entry pwdnen h l h l x h x h x h xxxx 1,5 power down mode exit pwdnex l h x x x x x x x x 1,6 self refresh entry srefen h l l l l h x x x x 1,7 self refresh exit srefex l h x x x x x x x x 1,8
hyb18t256321f?[20/22/25] ddr sgram pin configuration data sheet 18 rev. 1.52, 06-2004 05142004-zttv-e1oq 2.3.2 description of commands table 5 description of commands command description desel the desel function prevents new commands from being executed by the graphics sdram. the graphics sdram is effectively deselected. operations in progress are not affected. nop the nop command is used to perform a no operation to the graphics sdram, which is selected (cs is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. mrs the mode register is loaded via address inputs a0 - a11. for more details see sections chapter 3.5 . the mrs command can only be issued when all banks are idle and no bursts are in progress. a subsequent executable command cannot be issued until t mrd is met. emrs the extended mode register is loaded via address inputs a0 - a11. for more details see section chapter 3.4 . the emrs command can only be issued when all banks are idle and no bursts are in progress. a subsequent executable command cannot be issued until t mrd is met. act the act command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0 and ba1 inputs selects the bank, and the address provided in inputs a0 - a11 selects the row. this row remains active (or open) for accesses until a precharge (pre, rd/a, or wr/a command) is issued to that bank. a precharge must be issued before opening a different row in the same bank. rd the rd command is used to initiate a burst read access to an active row. the value on the ba0 and ba1 inputs selects the bank, and the address provided on inputs a2-a7, a9 selects the column location. the row will remain open for subsequent accesses. for rd commands the value on a8 is set low. rd/a the rd/a command is used to initiate a burst read access to an active row. the value on the ba0 and ba1 inputs selects the bank, and the address provided on inputs a2-a7, a9 selects the column location. the value on input a8 is set high. the row being accessed will be precharged at the end of the read burst. the same individual-bank precharge function is performed like it is described for the pre command. auto precharge ensures that the precharge is initiated at the earliest valid stage within the burst. the user must not issue a new act command to the same bank until the precharge time (t rp ) is completed. this time is determined as if an explicit pre command was issued at the earliest possible time as described in section chapter 3.10 . wr the wr command is used to initiate a burst write access to an active row. the value on the ba0 and ba1 inputs selects the bank, and the address provided on inputs a2-a7, a9 selects the column location. the row will remain open for subsequent accesses. for wr commands the value on a8 is set low. input data appearing on the dqs is written to the memory array depending on the value on the dm input appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to the memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed for that byte / column location. wr/a the wr/a command is used to initiate a burst write access to an active row. the value on the ba0 and ba1 inputs selects the bank, and the address provided on inputs a2-a7, a9 selects the column location. the value on input a8 is set high. the row being accessed will be precharged at the end of the write burst. the same individual-bank precharge function is performed which is described for the pre command. auto precharge ensures that the precharge is initiated at the earliest valid stage within the burst. the user is not allowed to issue a new act to the same bank until the precharge time (t rp ) is completed. this time is determined as if an explicit pre command was issued at the earliest possible time as described in section chapter 3.7 . input data appearing on the dqs is written to the memory array depending on the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to the memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte / column location.
hyb18t256321f?[20/22/25] ddr sgram pin configuration data sheet 19 rev. 1.52, 06-2004 05142004-zttv-e1oq pre the pre command is used to deactivate the open row in a particular bank. the bank will be available for a subsequent row access a specified time (t rp ) after the pre command is issued. inputs ba0 and ba1 select the bank to be precharged. a8/ap is set to low. once a bank has been precharged, it is in the idle state and must be activated again prior to any rd or wr commands being issued to that bank. a pre command will be treated as a nop if there is no open row in that bank, or if the previously open row is already in the process of precharging. preall the preall command is used to deactivate all open rows in the memory device. the banks will be available for a subsequent row access a specified time (t rp ) after the preall command is issued. once the banks have been precharged, they are in the idle state and must be activated prior to any read or write commands being issued. the preall command will be treated as a nop for those banks where there is no open row, or if a previously open row is already in the process of precharging. preall is issued by a pre command with a8/ap set to high. aref the aref is used during normal operation of the gddr3 graphics ram to refresh the memory content. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an aref command. the hyb18t256321f requires aref cycles at an average periodic interval of t refi (max)=7.8 s. to improve efficiency a maximum number of eight aref commands can be posted to one memory device (with t rfc from aref to aref) as described in section chapter 3.11 . this means that the maximum absolute interval between any aref command is 8 x 7.8s (62.4s). this maximum absolute interval is to allow the gddr3 graphics ram output drivers and internal terminators to recalibrate, compensating for voltage and temperature changes. all banks must be in the idle state before issuing the aref command. they will be simultaneously refreshed and return to the idle state after aref is completed. trfc is the minimum required time between an aref command and a following act/aref command. srefen the self refresh function can be used to retain data in the gddr3 graphics ram even if the rest of the system is powered down. when entering the self refresh mode by issuing the srefen command, the gddr3 graphics ram retains data without external clocking. the srefen command is initiated like an aref command except cke is disabled (low). the dll is automatically disabled upon entering self refresh mode and automatically enabled and reset upon exiting self refresh. (200 cycles must then occur before a rd command can be issued) the adress, command and data terminators remain on input signals except cke are ?don?t care?. if two gddr3 graphics rams share the same cimmand and address bus, self refresh max be entered only for the two devices at the sme time. srefex the srefex command is used to exit the self refresh mode. the dll is automatically enabled and resetted upon exiting. the procedure for exiting self refresh requires a sequence of commands. first clk and clk must be stable prior to cke going from low to high. once cke is high, the gddr3 graphics ram must receive only nop/desel commands until t xsnr is satisfied. this time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh, dll requirements and output calibration is to apply nops for 200 cycles before applying any other command to allow the dll to lock and the output drivers to recalibrate. pwdnen the pwdnen command enables the power down mode. it is entered when cke is set low together with a nop/desel. the cke signal is sampled at the rising edge of the clock. once the power down mode is initiated, all of the receiver circuits except clk and cke are gated off to reduce power consumption. the dll remains active (unless disabled before with emrs). all banks can be set to idle state or stay active. during power down mode, refresh operations cannot be performed; therefore the refresh conditions of the chip have to be considered and if necessary power down state has to be left to perform an autorefresh cycle. table 5 description of commands command description
hyb18t256321f?[20/22/25] ddr sgram pin configuration data sheet 20 rev. 1.52, 06-2004 05142004-zttv-e1oq pwdnex a cke high value sampled at a low to high transition of clk is required to exit power down mode. once cke is high, the gddr3 graphics ram must receive only nop/desel commands until t xpn is satisfied. after t xpn any command can be issued, but it has to comply with the state in which the power down mode was entered. dterdis data termination disable (bus snooping for rd commands) : the data termination disable command is detected by the device by snooping the bus for rd commands excluding cs . the gddr3 graphics ram will disable its data terminators when a rd command is detected. the terminators are disabled starting at cl - 1 clocks after the rd command is detected and the duration is 4 clocks. in a two rank system, both dram devices will snoop the bus for rd commands to either device and both will disable their terminators if a rd command is detected. the command and address terminators are always enabled. see figure 9 for an example of when the data terminators are disabled during a rd command. table 6 minimum delay from rd/a and wr/a to any other command (to another bank) with concurrent autoprecharge from command to command minimum delay to another bank (with concurrent autoprecharge) note wr/a rd or rd/a (wl + 2) . t ck + t wtr wr or wr/a 2 . t ck pre t ck act t ck rd/a rd or rd/a 2 . t ck wr or wr/a (cl + 4 - wl) . t ck pre t ck act t ck table 5 description of commands command description
hyb18t256321f?[20/22/25] ddr sgram pin configuration data sheet 21 rev. 1.52, 06-2004 05142004-zttv-e1oq 2.4 state diagram and truth tables 2.4.1 state diagram for one activated bank the following diagram shows all possible states and transitions for one activated bank. the other three banks of the graphics sdram are assumed to be in idle state. figure 3 state diagram for one bank note: mrs, emrs, auto refresh, self refresh and precharge power down are only allowed if all four banks are idle. idle self refresh power down active precharge auto refresh act pre wr/a rd/a pden pdex pdex pden mrs emrs sren srex active wr rd single bank all banks
hyb18t256321f?[20/22/25] ddr sgram pin configuration data sheet 22 rev. 1.52, 06-2004 05142004-zttv-e1oq 2.4.2 function truth table for more than one activated bank if there is more than one bank activated in the graphics sdram, some commands can be performed in parallel due to the chip?s multibank architecture. the following table defines for which commands such a scheme is possible. all other transitions are illegal. notes 1-11 define the start and end of the actions belonging to a submitted command. this table is based on the assumption that there are no other actions ongoing on bank n or bank m. if there are any actions ongoing on a third bank t rrd , t rtw and t wtr have to be taken always into account. 1. action activate starts with issuing the command and ends after t rcd 2. action write starts with issuing the command and ends t wr after the first pos. edge of clk following the last falling wdqs edge; exept for read, read/a. write, write/a ends t wtr after the first pos. edge of clk following the last falling wdqs edge. 3. action write/a starts with issuing the command and ends t wr after the first positive edge of clk following the last falling wdqs edge; exept for read, read/a. write, write/a ends t wtr after the first pos. edge of clk following the last falling wdqs edge. 4. action read starts with issuing the command and ends with the first positive edge of clk following the last falling edge of rdqs 5. action read/a starts with issuing the command and ends with the first positive edge of clk following the last falling edge of rdqs 6. action precharge and precharge all start with issuing the command and ends after t rp 7. during power down and self refresh only the exit commands are allowed 8. action auto refresh starts with issuing the command and ends after t rfc 9. actions mode register set and extended mode register set start with issuing the command and ends after t mrd 10. action power down exit starts with issuing the command and ends after t xpn 11. action self refresh exit starts with issuing the command and ends after t xsc 12. during action activate an act command on another bank is allowed considering t rrd , a pre command on another bank is allowed any time. wr, wr/a, rd and rd/a are always allowed. 13. during action write an act or a pre command on another bank is allowed any time. a new wr or wr/a command on another bank must be separated by at least one nop from the ongoing write. rd or rd/a are not allowed before t wtr is met. table 7 function truth table i current state ongoing action on bank n possible action in parallel on bank m active activate 1 act, pre, write, write/a, read, read/a 12 write 2 act, pre, write, write/a, read, read/a 13 write/a 3 act, pre, write, write/a, read 14 read 4 act, pre, write, write/a, read, read/a 15 read/a 5 act, pre, write, write/a, read, read/a 15 precharge 6 act, pre, write, write/a, read, read/a 12 precharge all 6 - power down entry 7 - idle activate 1 act power down entry 7 - auto refresh 8 - self refresh entry 7 - mode register set (mrs) 9 - extended mrs 9 - power down power down exit 10 - self refresh self refresh exit 11 -
hyb18t256321f?[20/22/25] ddr sgram pin configuration data sheet 23 rev. 1.52, 06-2004 05142004-zttv-e1oq 14. during action write/a an act or a pre command on another bank is allowed any time. a new wr or wr/a command on another bank has to be separated by at least one nop from the ongoing command. rd is not allowed before t wtr is met. rd/a is not allowed during an ongoing write/a action. 15. during action read and read/a an act or a pre command on another bank is allowed any time. a new rd or rd/a command on another bank has to be separated by at least one nop from the ongoing command. a wr or wr/a command on another bank has to meet t rtw . 2.4.3 function truth table for cke 1. cke n is the logic step at clock edge n; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the gddr3 graphics ram immediatly prior to clock edge n. 3. command is the command registered at clock edge n, and action is a result of command. 4. all states and sequences not shown are illegal or reserved. 5. desel or nop commands should be issued on any clock edges occuring during the t xsr period. a minimum of 200 clock cycles is required before applying any other valid command. table 8 function truth table ii (cke table) cke n-1 cke n current state command action l l power down x stay in power down self refresh x stay in self refresh l h power down desel or nop exit power down self refresh desel or nop exit self refresh 5 h l all banks idle desel or nop entry precharge power down bank(s) active desel or nop entry active power down all banks idle auto refresh entry self refresh
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 24 rev. 1.52, 06-2004 05142004-zttv-e1oq 3 functional description 3.1 clocks, cke, commands and addresses figure 4 clock, cke and command/address timings setup and hold timing for cke is equal to cmd and addr setup and hold timing. the dll ensures the alignment of dqs and clk. therefore the preferred operation mode for high frequencies is dll on. the dll frequency range is from 500 mhz down to 250 mhz. table 9 general timing parameters for -2.0 ns, -2.2 ns and -2.5 ns speed sorts parameter cas latency symbol limit values unit - 2.0 - 2.2 - 2.5 min max min max min max clock clock cycle time 7 t ck7 2.0 4.0 2.2 4.0 2.5 4.0 ns 6 t ck6 2.0 4.0 2.2 4.0 2.5 4.0 ns 5 t ck5 ? ? 2.7 4.0 3.0 4.0 ns system frequency 7 f ck7 250 500 250 455 250 400 mhz 6 f ck6 250 500 250 455 250 400 mhz 5 f ck5 ? ? 250 370 250 333 mhz clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck command, cke and address setup and hold times address/command/cke input setup time t is 0.75 ? 0.75 ? 0.85 ? ns address/command/cke input hold time t ih 0.75 ? 0.75 ? 0.85 ? ns address/command/cke input pulse width t ipw 0.85 ? 0.85 ? 0.85 ? t ck don't care clk# clk t ch t cl t ck cmd, addr, cke t ih t is t ipw
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 25 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.2 initialization the hyb18t256321f must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation or permanent damage to the device. the following sequence is highly recommended for power-up: 1. apply power (vdd, vddq, vref). apply vdd before or at the same time as v ddq , apply v ddq before or at the same time as v ref . maintain res=l and cs=h to ensure that all the dq ouputs will be in hiz state, all active terminations off and the dll off. all other pins may be undefined. 2. maintain stable conditions for 200 s minimum for the gddr3 graphics ram to power up. 3. after clock is stable, set cke to l. after t ats minimum set res to high. on the rising edge of res, the cke value is latched to determine the address and command bus termination value. if cke is sampled low the address termination value is set to zq / 2. if cke is sampled high, the address and command bus termination is set to zq. 4. after t ath minimum, set cke to high. 5. wait a minimum of 350 cycles to calibrate and update the address and command termination impedances. issue deselect on the command bus during these 350 cycles. 6. apply a precharge all command, followed by an extended mode register command after t rp is met and activate the dll. 7. issue an mode register set command after tmrd is met to reset the dll and define the operating parameters. 8. wait 200 cycles of clock input to lock the dll. no read command can be applied during this time. since the impedance calibration is already completed, the dll mimic circuitry can use the actual programmed driver impedance value. 9. issue a precharge all command or issue 4 single bank precharge commands, one to each of the 4 banks to place the chip in an idle state. 10. issue two or more auto refresh commands to update the driver impedance. figure 5 power up sequence table 10 reset timing parameters for -2.0, -2.2 and -2.5 speed sorts parameter symbol limit values unit notes - 2.0 - 2.2 - 2.5 min max min max min max res to cke setup time t ats 10?10?10?ns res to cke hold time t ath 10?10?10?ns clk# clk cke min. 200 s com. vdd vddq vref res t ats t ath pa em r t r p mrs t mrd arf a.c. arf pa t rfc t rfc t r p cycles min. 200 vdd and clk stable don't care pa: preall command a.c.: any command arf: auto refresh command t mrd cycles min. 350 des des mrs: mrs command with dll reset emr: emrs command des : deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 26 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.3 programmable impedance output drivers and active terminations 3.3.1 gddr3 io driver and termination the gddr3 sgram is equipped with programmable impedance output buffers and active terminations. this allows the user to match the driver impedance to the system impedance. to adjust the impedance of dq<0:31> and rdqs<0:3> , an external precision resistor (zq) is connected between the zq pin and vss. the value of the resitor must be six times the value of the desired impedance. for example, a 240 ? resistor is required for an output impedance of 40 ? . the range of zq is 210 ? to 270 ?, giving an output impedance range of 35 ? to 45 ? (one sixth the value of zq within 10%). res, clk and clk are not internally terminated. the value of zq is used to calibrate the internal dq termination resistors of dq<0:31>, wdqs<0:3> and dm<0:3>. the two termination values that are selectable using emrs[3:2] are zq / 4 and zq / 2. the value of zq is also used to calibrate the internal address command termination resistors. the inputs terminated in this manner are a<0:11>, cke, cs , ras , cas , we . the two termination values that are selectable upon power up (cke latched a the low to high transition of res) are zq/2 and zq. the signals res and clk/clk are not internally terminated. if no resistance is connected to zq, an internal default value of 240 ? will be used. in this case, no calibration will be performed. figure 6 output driver simplified schematic table 11 range of external resistance zq parameter symbol min nom max unit notes external resistance value zq 210 240 270 ? table 12 termination types and activation ball termination type termination activation clk, clk , rdqs<0:3>, zq, res no termination cke, cs , ras , cas , we , ba<0:1>, a<0:11> add / cmds always on dm<0:3>, wdqs<0:3>, dq always on dq<0:31> dq cmd bus snooping vssq vddq dq read to other rank output data read data enable zq/4 or zq/2 terminator when receiving zq/6 driver when transmitting
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 27 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.3.2 self calibration fo r driver and termination figure 7 termination update keep out time after autorefresh command to guarantee optimum driver impedanc e after power-up, the gddr3 sgram needs 350 cycles after the clock is applied and stable to calibrate the impedance upon power-up. the user can operate the part with fewer than 350 cycles, but optimal output impedance will not be guaranteed. the gddr3 graphics ram proceeds in the following manner for self calibration : the pmos device is calibrated against the external zq resistor value ( figure 8 ). first one pmos leg is calibrated against zq. the number of legs used for the terminators ( dq and add/cmd) and the pmos driver is represented in table 14 . next, one nmos leg is calibrated against the already calibrated pmos leg. the nmos driver uses 6 nmos legs. note: emrs[3:2] = 00 disables the add and cmd terminations as well. figure 8 represents a simplified schematic of the calibration circuits. first, the strength control bits are adjusted in such a way that the v ddq voltage is divided equaly between the pmos device and the zq resistor. the best bit table 13 termination update keep out time parameter symbol limit values unit notes - 2.0 - 2.2 - 2.5 min max min max min max termination update keep out time t ko 10?10?10?ns table 14 number of legs used for terminator and driver self calibration termination number of legs notes cke (at res) terminator add / cmd 0 zq/2 2 1zq1 emrs[3:2] dq 00 disabled 0 1 10 zq/4 4 11 zq/2 2 driver pmos zq/6 6 nmos zq/6 6 clk# clk don't care t ko com. arf: autorefresh arf add. dq keep out time
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 28 rev. 1.52, 06-2004 05142004-zttv-e1oq pattern will cause the comparator to switch the pmos match signal output value. in a second step, the nfet is calibrated against the already calibrated pfet. in the same manner, the best control bit combination will cause the comparator to switch the nmos match signal output value. figure 8 self calibration of pmos and nmos legs 3.3.3 dynamic switching of dq terminations the gddr3 graphics ram will disable its data terminators when a read or dterdis command is detected. the terminators are disabled starting at cl - 1 clocks after the read / dterdis command is detected and the duration is 4 clocks. in a two rank system, both devices will snoop the bus for a read / dterdis command to either device and both will disable their terminators if a read / dterdis command is detected. the address and command terminators are always enabled. figure 9 odt disable timing during a read command vddq strength control [2:0] vssq match vddq / 2 zq pmos calibration vssq vddq strength control [2:0] vssq match vddq / 2 nmos calibration clk# clk rd n/d n/d com . n/d n/d n/d n/d n/d 01234567 8 b / c addr. cas latency = 5 rdqs dq b / c: bank / column address rd: read d3 d2 d1 d0 9 n/d n/d data terminations are disabled dq termination don't care dx: data from b / c com.: command addr.: address b / c n/d: nop or deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 29 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.3.4 output impedance and terminati on dc electrical characteristics the driver and termination impedances are determined by applying v ddq/2 nominal (1.0 v) at the corresponding input / output and by measuring the current flowing into or out of the device. v ddq is set to the nominal value of 2.0 v. (see table 1 ) i oh is the current flowing out of dq when the pull-up transistor is activated and the dq termination disabled. i ol is the current flowing into dq when the pull-down transistor is activated and the dq termination disabled. i tcah(zq) is the current flowing out of the termination of commands and addresses for a zq termination value. note: 1: measurement performed with v ddq =2.0 v (nominal see table 1 ) and by applying v ddq/2 (1.0 v) at the corresponding input / output. 0c t c 85c. table 15 dc electrical characteristics parameter nom. unit notes zq value 240 ? min max i oh zq/6 20.5 25.0 ma 1 i ol zq/6 20.5 25.0 ma 1 i tcah(zq) zq 3.4 4.2 ma 1
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 30 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.4 extended mode regi ster set command (emrs) figure 10 extended mode register bitmap the extended mode register is used to set the output driver impedance value, the termination impedance value, the write recovery time value for write with autoprecharge. it is used as well to enable/disable the dll, to issue the vendor id and to enable/disable the low power mode. there is no default value for the extended mode register. therefore it must be written after power up to operate the gddr3 graphics ram. the extended mode register can be programmed by performing a normal mode register set operation and setting the ba0 bit to high. all other bits of the emr register are reserved and should be set to low. the extended mode register must be loaded when all banks are idle and no burst are in progress. the controller must wait the specified time t mrd before initiating any subsequent operation). the timing of the emrs command operation is equivalent to the timing of the mrs command operation. figure 11 extended mode register bitmap 1. these settings are for debugging purposes only. 2. default termination values at power up. 3. the odt disable function disables all terminators on th device. 4. if the user activates bits in an extended mode register in an optional field, either the optional field is activated (if option implemented on the device) or no action is taken by the device (if ioption not implemented). 5. wr (write recovery time for write with autoprecharge) in clock cycles is calculated by dividing twr (in ns) and rounding up to the next integer (wr[cycles]=twr[ns]/tck[ns]). the mode register must be programmed to this value. clk# clk ras# cke cas# we# a0-a11 ba0 1 don't care cod: code to be loaded into the register cs# cod ba1 0 data z ba1 ba0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 01 a11 a10 dll v rfu wr rtt a11 0 1 low power enable disable a2 0 1 a3 0 0 0 1 1 1 odt disabled rfu termination zq / 4 zq / 2 (default) 2) 1 output driver impedance autocal 35 ? 1) 0 40 ? 1) 45 ? 1) 1 a0 a1 1 1 0 0 0 1 wr 3 4 05 6 1 a4 a5 1 1 0 0 0 lp a10 0 1 vendor id on off a6 0 1 dll enable enable disable
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 31 rev. 1.52, 06-2004 05142004-zttv-e1oq figure 12 extended mode register set timing 3.4.1 dll enable the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after having disabled the dll. (when the device exits self-refresh mode, the dll is enabled automatically). anytime the dll is enabled, 200 cycles must occur before a read command can be issued. 3.4.2 wr the wr parameter is programmed using the register bits a4 and a5. this integer parameter defines as a number of clock cycles the write recovery time in a write with autoprecharge operation. the following inequality has to be complied with : wr * t ck t wr , where t ck is the clock cycle time as defined in table 8 and t wr the write recovery time as defined in table 23 . note: refer to figure 3.7.4 for more details. 3.4.3 termination rtt the data termination, rtt , is used to set the value of the internal terminaton resistors. the gddr iii dram supports zq / 4 and zq / 2 termination values. the termination may also be disabled for testing and other purposes. 3.4.4 output driver impedance the output driver impedance extended mode register is used to set the value of the data output driver impedance. when the autocalibration is used, the output driver impedance is set nominally to zq / 6. 3.4.5 low power when the low power extended mode register is set, the device enters a low power mode of operation. this mode is not enabled for the hyb18t256321f. setting this bit to high will have no effect on the behavior of the gddr3 dram. table 16 emrs timing parameters for ?2.0, ?2.2 and ?2.5 speed sorts parameter symbol limit values unit notes - 2.0 - 2.2 - 2.5 min max min max min max mode register set cycle time t mrd 4?4?4? t ck clk# clk don't care pa emrs nop a.c. nop t rp t mrd command emrs: extended mrs command pa: preall command a.c.: any command nop
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 32 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.4.6 vendor code and revision iden tification the manufacturer vendor code is selected by issuing an extended mode register set command with bit a10 set to 1 and bits a0-a9 and a11 set to the desired value. when the vendor code function is enabled the gddr3 dram will provide the infineon vendor code on dq[3:0] and the revision identification on dq[7:4]. the code will be driven onto the dq bus after t ridon following the emrs command that sets a10 to 1. the vendor code and revision id will be driven on dq[7:0] until a new emrs command is issued with a10 set back to 0. after t rdoff following the second emrs command, the data bus is driven back to high. this second emrs command must be issued before initiating any subsequent operation. violating this requirement will result in unspecified operation. note: please refer to revision release note for revision id value figure 13 timing of vendor code and revision id generation on dq[7:0] table 17 revision id and vendor code revision identification infineon vendor code dq[7:4] dq[3:0] xxxx 0010 table 18 vendor code and revision id timing parameters for -2.0, -2.2 and -2.5 speed sorts parameter symbol limit values unit notes - 2.0 - 2.2 - 2.5 min max min max min max emrs to dq on time t ridon ?20?20?20ns emrs to dq off time t ridoff ?20?20?20ns clk# clk n/d n/d com. n/d n/d n/d n/d 01234567 8 add a[9:0], a11 9 10 n/d n/d rdqs dq[7:0] a10 n/d add emrs emrs t ridon vendor code and revision id t ridoff emrs: extended mode register set command add: address don't care n/d: nop or deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 33 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.5 mode register set command (mrs) figure 14 mode register set command the mode register stores the data for controlling the operating modes of the memory. it programs read latency, test mode, dll reset and the value of the write latency. there is no default value for the mode register; therefore it must be written after power up to operate the gddr3 graphics ram. during a mode register set command the address inputs are sampled and stored in the mode register. t mrd must be met before any command can be issued to the graphics sdram. the mode register contents can only be set or changed when the graphics sdram is in idle state. figure 15 mode register bitmap note: the dll reset command is self-clearing clk# clk ras# cke cas# we# a0-a11 ba0 0 don't care cod: code to be loaded into the register cs# cod ba1 0 dll tm cas latency dll reset 00 bl cas latency bt ba1 ba0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a11 a10 wl a8 0 1 dll reset yes no write latency burst length b l a2 a1 a0 all others 010 rfu 4 latency a6 a5 a4 all others 6 110 rfu 100 5 101 1 1 1 7 rfu a7 0 1 mode normal testmode testmode a3 0 1 bt sequential rfu burst type wl a11 a10 a9 all others 4 100 2 010 3 011 rfu a0 note: 1) the dll reset command is self-clearing
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 34 rev. 1.52, 06-2004 05142004-zttv-e1oq figure 16 mode register set timing 1. this value of t mrd applies only to the case where the ?dll reset? bit is not activated. 2. t mrd is defined from mrs to any other command as read. 3.5.1 burst length read and write accesses to the gddr3 graphics ram are burs t oriented with burst length 4. this value must be programmed using the mode register set command (a0 .. a2). the burst length determines the number of column locations that can be accessed for a given read or write command. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block if a boundary is reached. the block is uniquely selected by a2-ai where ai is the most significant bit for a given configuration. the starting location within this block is determined by the two least significant bits a0 and a1 which are set internally to the fixed value of zero each. reserved states should not be used, as unknow operation or incompatibility with future versions may result. 3.5.2 burst type accesses within a given bank must be programmed to be sequential. this is done using the mode register set command (a3) . this device does not support the burst interleave mode. the value applied at the balls a0 and a1 for the column address is ?don?t care?. table 19 mrs timing parameters for ?2.0, ?2.2 and ?2.5 speed sorts parameter symbol limit values unit notes - 2.0 - 2.2 - 2.5 min max min max min max mode register set cycle time t mrd 4?4?4?t ck 1, 2 mode register set to read timing t mrdr 12?12?12?t ck 1 clk# clk pa mrs nop a.c. nop t rp t mrd command nop rd nop don't care mrs: mrs command pa: preall command a.c.: any other command as read t mrdr rd: read command table 20 burst type burst length starting column address order of accesses within the burst type = sequential 4a1 a0 x x 0-1-2-3
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 35 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.5.3 cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data as shown on figure 31 . the latency can be set to 5 to 7 clocks as shown in figure 15 . if a read command is registered at clock edge n, and the latency is m clocks, the data will be available nominally concident with clock edge n+m. refer to appendix, figure 42 , for values of operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. 3.5.4 write latency the write latency, wl, is the delay, in clock cycles, between the registration of a write command and the availability of the first bit of input data as shown in figure 21 . wl can be set from 2 to 4 clocks depending on the operating frequency. setting the write latency to 2 or 3 clocks will cause the device to enable the data input receivers on all act commands. 3.5.5 test mode the normal operating mode is selected by issuing a mode register set command with bit a7 set to zero and bits a0-a6 and a8-a11 set to the desired value. 3.5.6 dll reset the normal operating mode is selected by issuing a mode register set command with bit a8 set to zero and bits a0-a7 and a9-a11 set to the desired values. a dll reset is initiated by issuing a mode register set command with bit a8 set to one and bits a0-a7 and a9-a11 set to the desired values. the gddr3 sgram returns automatically in the normal mode of operations once the dll reset is completed.
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 36 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.6 bank / row activation (act) figure 17 activating a specific row before a read or write command can be issued to a bank, a row in that bank must be opened. this is accomplished via the act command, which selects both the bank and the row to be activated. after opening a row by issuing an act command, a read or write command may be issued after t rcd to that row. a subsequent act command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). the minimum time interval between successive act commands to the same bank is defined by t rc . a subsequent act command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive act commands to different banks is defined by t rrd . there is a minimum time t ras between opening and closing a row. figure 18 bank activation timing clk# clk ras# cke cas# we# a0-a11 ba0-ba1 ra ba ra: row address ba: bank address don't care cs# clk# clk t rrd t rcd t ras t rc act act r/w com. pre act row row col a0-a11 a8 row b.x b.y b.y ba0, ba1 b.y b.y row: row address col: column address don't care b.x: bank x b.y: bank y r/w: read or write command pre: precharge command act: activate command
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 37 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.7 writes (wr) 3.7.1 write basic information figure 19 write command write bursts are initiated with a wr command, as shown in figure 19 . the column and bank addresses are provided with the wr command, and auto precharge is either enabled or disabled for that access. the length of the burst initiated with a wr command is always four. there is no interruption of wr bursts. the two least significant address bits a0 and a1 are ?don?t care?. for wr commands with autoprecharge the row being accessed is precharged t wr/a after the completion of the burst. if t ras (min) is violated the begin of the internal autoprecharge will be performed one cycle after t ras (min) is met. t wr/a can be programmed in the mode register. choosing high values for t wr/a will prevent the chip to delay the internal autoprecharge in order to meet t ras (min). during wr bursts data will be registered with the edges of wdqs. the write latency can be programmed during extended mode register set. the first valid data is registered with the first valid rising edge of wdqs following the wr command. the externally provided wdqs must switch from high to low at the beginning of the preamble. there is also a postamble requirement before the wdqs returns to high. the wdqs signal can only transition when data is applied at the chip input and during pre- and postambles. t dqss is the time between wr command and first valid rising edge of wdqs. nominal case is when wdqs edges are aligned with edges of external clk. minimum and maximum values of t dqss define early and late wdqs operation. any input data will be ignored before the first valid rising wdqs transition. t dqsl and t dqsh define the width of low and high phase of wdqs. the sum of t dqsl and t dqsh has to be t ck . table 21 act timing parameters for ?2.0, ?2.2 and ?2.5 speed sorts parameter symbol limit values unit notes - 2.0 - 2.2 - 2.5 min max min max min max row cycle time t rc 37.2 ? 39.6 ? 45.0 ? ns row active time t ras 24.0 8 x t refi 26.2 8 x t refi 30.0 8 x t refi ns act(a) to act(b) command period t rrd 8.0 ? 8.8 ? 10.0 ? ns row to column delay time for reads t rcdrd 16.0 ? 17.5 ? 17.5 ? ns row to column delay time for writes t rcdwr t rcdwr(min) = t rcdrd(min) - (wl + 1) x t ck(min) ns clk# clk ras# cke cas# we# a2-a7, a9 ba0-ba1 ca ba ca: column address ba: bank address don't care a0, a1 a10-a11 a8 ap ap: autoprecharge cs#
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 38 rev. 1.52, 06-2004 05142004-zttv-e1oq back to back wr commands are possible and produce a continuous flow of input data. there must be one nop cycle between two back to back wr commands. any wr burst may be followed by a subsequent rd command. figure 3.7.5 shows the timing requirements for a wr followed by a rd. a wr may also be followed by a pre command to the same bank. t wr has to be met as shown in figure 3.7.8 . setup and hold time for incoming dqs and dms relative to the wdqs edges are specified as t ds and t dh . dq and dm input pulse width for each input is defined as t dipw . the input data is masked if the corresponding dm signal is high. all timing parameters are defined with graphics dram terminations on. figure 20 basic write burst / dm timing note: : wdqs can only transition when data is applied at the chip input and during pre- and postambles table 22 mapping of wdqs and dm signals wdqs data mask signal controlled dqs wdqs0 dm0 dq0 - dq7 wdqs1 dm1 dq8 - dq15 wdqs2 dm2 dq16 - dq23 wdqs3 dm3 dq24 - dq31 dq t dh dmx dmx: represents one dm line don't care t dh t ds t dh t ds data masked data masked d0 d1 d2 d3 clk# clk t wpre t wpst t dqss nominal preamble postamble min(t dqss ) max(t dqss ) t dqss t ds t dqsl t dqsh t dqsh t dipw t dipw nominal wdqs late wdqs early wdqs wdqs wdqs wdqs
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 39 rev. 1.52, 06-2004 05142004-zttv-e1oq table 23 wr timing parameters for ?2.0, ?2.2 and ?2.5 speed sorts parameter symbol limit values unit notes - 2.0 - 2.2 - 2.5 min max min max min max cas(a) to cas(b) command period t ccd 2?2?2? t ck 1) 1) t ccd is either for gapless consecutive writes or gapless consecutive reads write cycle timing parameters for data and data strobe write command to first wdqs latching transition t dqss wl - 0.25 wl +0.25 wl - 0.25 wl +0.25 wl - 0.25 wl +0.25 t ck data-in and data mask to wdqs setup time t ds 0.375 ? 0.375 ? 0.425 ? ns 2) 2) timing parameters defined with graphics dram terminations on. data-in and data mask to wdqs hold time t dh 0.375 ? 0.375 ? 0.425 ? ns 2) data-in and dm input pulse width (each input) t dipw 0.45 ? 0.45 ? 0.45 ? t ck wdqs input low pulse width t dqsl 0.45 ? 0.45 ? 0.45 ? t ck 3) 3) t dqsl . and t dqsh apply for the write preamble and postamble as well. wdqs input high pulse width t dqsh 0.45 ? 0.45 ? 0.45 ? t ck 3) wdqs write preamble time t wpre 0.75 1.25 0.75 1.25 0.75 1.25 t ck wdqs write postamble time t wpst 0.75 1.25 0.75 1.25 0.75 1.25 t ck write to read command delay t wtr 6.0 ? 6.6 ? 7.5 ? ns 2)4) 4) twtr and t wr start at the first rising edge of clk after the last valid (falling) wdqs edge of the slowest wdqsx signal write recovery time t wr 11.0 ? 11.0 ? 12.5 ? ns 2)4)
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 40 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.7.2 write - basic sequence figure 21 write burst basic sequence 1. shown with nominal value of t dqss. 2. wdqs can only transition when data is applied at the chip input and during pre- and postambles. 3. when nops are applied on the command bus, the wdqs and the dq busses remain stable high. 4. when dess are applied on the command bus, the status of the wdqs and dq busses is unknown. clk# clk wr des des com . n/d des des des des 01234567 8 b/c addr. wl = 2 des dq wdqs wl = 4 wdqs dq d0 d3 d2 d1 d0 d3 d2 d1 wr nop nop com . n/d nop nop nop nop b/c addr. wl = 2 nop dq wl = 4 wdqs dq d0 d3 d2 d1 d0 d3 d2 d1 wr: write d#: data to b / c b / c: bank / column address com.: command addr.: address b / c wl: write latency don't care nop: no operation des: deselect n/p: nop or des
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 41 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.7.3 write - consecutive bursts 3.7.3.1 gapless bursts figure 22 gapless write bursts 1. shown with nominal value of t dqss 2. the second wr command may be either for the same bank or another bank 3. wdqs can only transition when data is applied at the chip input and during pre- and postambles dq wl = 2 wdqs clk# clk wr n/d des com. n/d des des des des 01234567 8 b/cx addr. wr 9 des b/cy wl = 3 dq wdqs wl = 4 dq wdqs b / cx: bank / column address x dx#: data to b / cx com.: command addr.: address b / c b / cy: bank / column address y dy#: data to b / cy wl: write latency dx2 dx1 dx3 dx0 dy3 dy0 dy1 dy2 dx2 dx1 dx3 dx0 dy3 dy0 dy1 dy2 dx2 dx1 dx3 dx0 dy3 dy0 dy1 dy2 don't care wr: write des: deselect n/d: nop / deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 42 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.7.3.2 bursts with gaps figure 23 consecutive write bursts with gaps 1. shown with nominal value of t dqss. 2. the second wr command may be either for the same bank or another bank. 3. wdqs can only transition when data is applied at the chip input and during pre- and postambles. clk# clk wr n/d com . n/d des des des des 01234567 8 b/cx addr. b/cy 9 wr des wdqs wdqs wl = 2 dq dq wl = 3 dq wl = 4 wdqs b / cx: bank / column address x wr: write dx#: data to b / cx com.: command addr.: address b / c b / cy: bank / column address y dy#: data to b / cy wl: write latency dx1 dx2 dy1 dy2 dx3 dx0 dy0 dy3 dx1 dx2 dy1 dy2 dx3 dx0 dy0 dy3 dx1 dx2 dy1 dy2 dx3 dx0 dy0 dy3 10 des des don't care des: deselect n/d: nop / deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 43 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.7.4 write with autoprecharge figure 24 write with autoprecharge 1. shown with nominal value of t dqss 2. t wr/a starts at the first rising edge of clk after the last valid edge of wdqs. 3. t rp starts after t wr/a has been expired. 4. when issuing a wr/a command please consider that the t ras requirement also must be met at the beginning of t rp 5. t wr/a * t cyc t wr 6. wdqs can only transition when data is applied at the chip input and during pre- and postambles 012345678 don't care wr/a: write with auto-precharge d#: data to b / c com.: command addr.: address b / c b / c: bank / column address wl: write latency clk# clk wr/a des des com. n/d des des des b/c a9, a7-a2 des des des des a8 910 wdqs t wr/a =3 wl = 2 dq begin of autoprecharge wl = 3 wdqs t wr/a =3 dq begin of autoprecharge t ras min satisfied wl = 4 wdqs dq t wr/a =3 begin of autoprecharge t ras min satisfied t rp d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 t ras min satisfied t rp t rp des: deselect n/d: nop or deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 44 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.7.5 write followed by read figure 25 write followed by read 1. shown with nominal value of t dqss. 2. the rd command may be either for the same bank or another bank. 3. wdqs can only transition when data is applied at the chip input and during pre- and postambles. dq wl = 2 t wtr wdqs wl = 3 dq t wtr wdqs clk# clk 01234567 8 9 wr des des com. n/d addr. des b/c b/c des des des wr des des n/d des des b/c b/c des rd n/d don't care wr: write d#: data to b / cx com.: command addr.: address b / c b / c: bank / column address wl: write latency rd: read wdqs wl = 4 dq t wtr wr des des n/d des des des b/c b/c des rd d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 rd des des des des: deselect n/d: nop / deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 45 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.7.6 write followed by dterdis figure 26 write command followed by dterdis 1. write shown with nominal value of t dqss. 2. wdqs can only transition when data is applied at the chip input and during pre- and postambles 3. a margin of one clock has been introduced in order to make sure that the data termination are still on when the last write data reaches the memory. 4. the minimum distance between write and dterdis is (wl -cl + 4) clocks and always bigger than or equal to 1. for (cl=6 / wl=2) and (cl=7 / wl=3) as well as for (cl=7 / wl=2) the minimum distance between write and dterdis is set to 1 clock. please refer to table below : dq wl = 2 wdqs wl = 3 dq wdqs clk# clk 01234567 8 9 wr des des com. addr. des b/c des des des wr des des des des b/c des des don't care wr: write d#: data to b / cx com.: command addr.: address b / c b / c: bank / column address wl: write latency dtd: dterdis wdqs wl = 4 dq wr des des n/d des des b/c des d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 des des des cl = 6 des des des dtd dtd cl = 6 cl = 5 cl: cas latency data termination off dtd des: deselect n/d: nop or deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 46 rev. 1.52, 06-2004 05142004-zttv-e1oq table 24 wl / cl wl \ cl 5 6 7 2111 3211 4321
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 47 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.7.7 write with autoprecharge followed by read / read with autoprecharge figure 27 write with autoprecharge followed by read or read with autoprecharge on another bank 1. shown with nominal value of t dqss. 2. the rd command is only allowed for another activated bank 3. twr/a is set to 3 in this example 4. wdqs can only transition when data is applied at the chip input and during pre- and postambles clk# clk wr/a des des com. n/d 01234567 8 a9, a2-a7 des b/c b/c 9 des a8 rd rd/a des des wr/a: write with autoprecharge b / c: bank / column address rd rd/a: read or read with autoprecharge don't care d#: data to b / cx com.: command addr.: address b / c wl: write latency 0: rd, 1: rd/a dq wl = 2 t wr/a t rp wdqs t wtr dq wl = 3 wdqs t wtr t wr/a t rp dq wl = 4 wdqs t wtr t wr/a t rp wr/a des des n/d des des des b/c b/c des des a8 rd rd/a a9, a2-a7 com. wr/a des des n/d des des des b/c b/c des a8 rd rd/a a9, a2-a7 com. d0 d3 d2 d1 begin of autoprecharge des des d0 d3 d2 d1 begin of autoprecharge d0 d3 d2 d1 begin of autoprecharge des: deselect n/d: nop or deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 48 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.7.8 write followed by precharge on same bank figure 28 write followed by precharge on same bank 1. shown with nominal value of t dqss. 2. wr and pre commands are to same bank 3. t ras requirement must also be met before issuing pre command 4. wdqs can only transition when data is applied at the chip input and during pre- and postambles clk# clk wr des com. n/d des des 01234567 8 addr. des b/c 9 des pre b des des dq wdqs wl = 2 t wr t rp dq wdqs wl = 3 t wr don't care wr: write dx#: data to b / cx com.: command addr.: address b / c b / c: bank / column address dy#: data to b / cy wl: write latency pre: precharge wr des des n/d des des des b/c des pre b des wr des des n/d des des des b/c des pre b des dq wdqs wl = 4 d0 d3 d2 d1 d0 d3 d2 d1 d0 d3 d2 d1 t wr des t rp t rp des des 10 n/d: nop or deselect des: deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 49 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.8 reads (rd) 3.8.1 read - basic information figure 29 read command read bursts are initiated with a rd command, as shown in figure 29 . the column and bank addresses are provided with the rd command and autoprecharge is either enabled or disabled for that access. the length of the burst initiated with a rd command is always four. there is no interruption of rd bursts. the two least significant start address bits are ?don?t care?. if autoprecharge is enabled, the row being accessed will start precharge at the completion of the burst. the begin of the internal autoprecharge will always be one cycle after t ras (min) is met. during rd bursts the memory device drives the read data edge aligned with the rdqs signal which is also driven by the memory. after a programmable cas latency of 5, 6 or 7 the data is driven to the controller. rdqs leaves high state one cycle before its first rising edge (rd preamble t rpre ). after the last falling edge of rdqs a postamble of t rpst is performed. t ac is the time between the positive edge of clk and the appearance of the corresponding driven read data. the skew between rdqs and the crossing point of clk/clk is specified as t dqsck . t ac and t dqsck are defined relatively to the positive edge of clk. t dqsq is the skew between a rdqs edge and the last valid data edge belonging to the rdqs edge. t dqsq is derived at each rdqs edge and begins with rdqs transition and ends with the last valid transition of dqs. t qhs is the data hold skew factor and t qh is the time from the first valid rising edge of rdqs to the first conforming dq going non-valid and it depends on t hp and t qhs . t hp is the minimum of t cl and t ch . t qhs is effectively the time from the first data transition (before rdqs) to the rdqs transition. the data valid window is derived for each rdqs transition and is defined as t qh minus t dqsq . after completion of a burst, assuming no other commands have been initiated, data will go high-z and rdqs will go high. back to back rd commands are possible producing a continuous flow of output data. there has to be one nop cycle between back to back rd commands. any rd burst may be followed by a subsequent wr command. the minimum required number of nop commands between the rd command and the wr command ( t rtw ) depends on the programmed read latency and the programmed write latency t rtw (min)= (cl+4-wl) chapter 3.8.5 shows the timing requirements for rd followed by a wr with some combinations of cl and wl. a rd may also be followed by a pre command. since no interruption of bursts is allowed the minimum time between a rd command and a pre is two clock cycles as shown in chapter 3.8.6 . all timing parameters are defined with controller terminations on. clk# clk ras# cke cas# we# a2-a7, a9 ba0-ba1 ca ba ca: column address ba: bank address don't care a0, a1 a10-a11 a8 ap ap: autoprecharge cs#
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 50 rev. 1.52, 06-2004 05142004-zttv-e1oq figure 30 basic read burst timing 1. the gddr3 sgram switches off the dq terminations one cycle before data appears on the busand drives the data bus high. 2. the gddr3 sgram drives the data bus high one cycle after the last data driven on the bus before switching the termination on again. 1. t ccd is either for gapless consecutive reads or gapless consecutive writes. table 25 read timing parameters for -2.0 ns, -2.2 ns and -2.5 ns speed sorts parameter symbol limit values unit note - 2.0 - 2.2 - 2.5 min max min max min max cas (a) to cas (b) command period t ccd 2?2?2?t ck 1 read to write command delay t rtw t rtw (min)= (cl+4-wl) t ck 2 read cycle timing parameters for data and data strobe data access time from clock t ac ?0.4 0.4 ?0.45 0.45 ?0.5 0.5 ns 4 read preamble t rpre 0.75 1.25 0.75 1.25 0.75 1.25 t ck read postamble t rpst 0.75 1.25 0.75 1.25 0.75 1.25 t ck data-out high impedance time from clk t hz t acmin t acmax t acmin t acmax t acmin t acmax n s 4 data-out low impedance time from clk t lz t acmin t acmax t acmin t acmax t acmin t acmax n s 4 rdqs edge to clock edge skew t dqsck -0.4 +0.4 -0.45 +0.45 -0.5 +0.5 ns 4 rdqs edge to output data edge skew t dqsq ? 0.225 ? 0.25 ? 0.28 ns 4 data hold skew factor t qhs 0 0.225 0 0.250 0 0.280 ns 4 data output hold time from rdqs t qh t hp ? t qhs t hp ? t qhs t hp ? t qhs ns 4 minimum clock half period t hp 0.45 ? 0.45 ? 0.45 ? t ck 3 t rpst rdqs don't care all dqs collectively clk# clk t ch t cl t qh t dqsq t dqsck t ac t rpre t ck t hp t dqsq t qhs dq (first data valid) dq (last data valid) d0 d1 d2 d3 data valid window t lz t hz d0 d1 d2 d3 d0 d1 d2 d3 hi-z : not driven by ddriii sgram preamble postamble
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 51 rev. 1.52, 06-2004 05142004-zttv-e1oq 2. please round up t rtw to the next integer of t ck . 3. t hp is the minimum of t cl and t ch 4. timing parameters defined with controller terminations on. 3.8.2 read - basic sequence figure 31 read burst 1. shown with nominal t ac and t dqsq 2. rdqs will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of rdqs 3. the dq terminations are switched off 1 cycle before the first read data and on again 1 cycle after the last read data clk# clk rd n/d n/d com . n/d n/d n/d n/d n/d 01234567 8 b / c addr. cas latency = 6 rdqs dq cas latency = 5 rdqs dq don't care n/d n/d 9 d3 d2 d1 d0 d3 d2 d1 d0 b / c: bank / column address rd: read dx: data from b / c com.: command addr.: address b / c dqs : terminations off rdqs : not driven n/d: nop or deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 52 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.8.3 consecutive read bursts 3.8.3.1 gapless bursts figure 32 gapless consecutive read bursts 1. the second rd command may be either for the same bank or another bank 2. shown with nominal t ac and t dqsq 3. example applies only when read commands are issued to same device 4. rdqs will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of rdqs 5. the dq terminations are switched off 1 cycle before the first read data and on again 1 cycle after the last read data clk# clk n/d n/d com. n/d n/d n/d 234567 8 b/cx addr. 9 cas latency = 6 rdqs rdqs dq dq dx2 dx1 dx3 dy0 dy1 dy2 dy3 dx0 cas latency = 5 don't care 10 dx2 dx1 dx3 dy0 dy1 dy2 dy3 dx0 n/d n/d 11 b / cx: bank / column address x rd: read dx#: data from b / cx com.: command addr.: address b / c b / cy: bank / column address y dy#: data from b / cy dqs : terminations off rdqs : not driven 01 rd n/d n/d n/d rd n/d: nop or deselect b/cy
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 53 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.8.3.2 bursts with gaps figure 33 consecutive read bursts with gaps 1. the second rd command may be either for the same bank or another bank 2. rdqs will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of rdqs. 3. the dq terminations are switched off 1 cycle before the first read data and on again 1 cycle after the last read data clk# clk rd n/d n/d com. n/d n/d n/d n/d n/d 01234567 8 b/cx addr. rd b/cy 9 cas latency = 5 cas latency = 6 rdqs rdqs dq dq 10 n/d n/d dx0 dx1 dx2 dx3 dy0 dy1 dy2 dy3 dx0 dx1 dx2 dx3 dy0 dy1 dy2 don't care b / cx: bank / column address x rd: read dx#: data from b / cx com.: command addr.: address b / c b / cy: bank / column address y dy#: data from b / cy dqs : terminations off rdqs : not driven
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 54 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.8.3.3 read followed by dterdis figure 34 read command followed by dterdis 1. at least 3 nops are required between a read command and a dterdis command in order to avoid contention on the rdqs bus in a 2 rank system. 2. cas latency 5 is used as an example. 3. the dq terminations are switched off (cl-1) clock periods after the dterdis command for a duration of (bl/2 + 2 ) clocks. 4. the dashed lines (rdqs bus) describe the rdqs behavior in the case where the dterdis command corresponds to a read command applied to the second graphics dram in a 2 rank system. in this case, rdqs would be driven by the second graphics dram. clk# clk rd n/d com. n/d n/d n/d n/d n/d 01234567 8 b/cx addr. 9 cas latency = 5 10 n/d n/d don't care b / cx: bank / column address x rd: read dx#: data from b / cx com.: command addr.: address b / c dqs : terminations off rdqs : not driven n/d n/d 11 12 n/d dtd rdqs dq dx0 dx1 dx2 dx3 rd n/d com. n/d n/d n/d n/d b/cx addr. cas latency = 5 n/d n/d n/d n/d n/d rdqs dq dx0 dx1 dx2 dx3 dtd n/d n/d n/d 13 dtd: dterdis des: deselect n/d: nop or deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 55 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.8.4 read with autoprecharge figure 35 read with autoprecharge 1. when issuing a rd/a command , the t ras requirement must be met at the beginning of autoprecharge 2. shown with nominal t ac and t dqsq 3. rdqs will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of rdqs 4. the dq terminations are switched off 1 cycle before the first read data and on again 1 cycle after the last read data 5. t ras lockout support clk# clk rd/a n/d n/d com. n/d n/d n/d n/d n/d n/d 01234567 8 a8 b / c a9, a7-a2 cas latency = 6 dq cas latency = 5 dq rdqs rdqs d3 d2 d1 d0 d3 d2 d1 d0 bl / 2 t rp begin of autoprecharge don't care rd/a: read with auto-precharge b / c: bank / column address dx: data from b / c com.: command addr.: address b / c dqs : terminations off rdqs : not driven n/d: nop or deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 56 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.8.5 read followed by write figure 36 read followed by write 1. shown with nominal t ac , t dqsq and t dqss 2. rdqs will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of rdqs 3. the dq terminations are switched off 1 cycle before the first read data and on again 1 cycle after the last read data 4. wdqs can only transition when data is applied at the chip input and during pre- and postambles 5. the write command may be either on the same bank or on another bank clk# clk com. 01234567 8 addr. 9 10 don't care 11 rd des des des des b/cr des des rd des des des des b/cr des des des cas latency = 5 t rtw write latency = 3 wdqs rdqs dq cas latency = 6 t rtw write latency = 4 wdqs rdqs dq d3r d2r d1r d0r des wr b/cw d3w d2w d1w d0w d3r d2r d1r d0r d2w d1w d0w des b/cw wr dxr: read data from b / c com.: command addr.: address b / c dxw: write data from b / c b / cw: bank / column address for write b / cr: bank / column address for read rd: read wr: write dqs : terminations off rdqs : not driven des des des des des des: deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 57 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.8.6 read followed by precharge on the same bank figure 37 read followed by precharge on the same bank 1. t ras requirement must also be met before issuing pre command 2. rd and pre commands are applied to the same bank. 3. shown with nominal t ac and t dqsq 4. rdqs will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of rdqs clk# clk rd n/d n/d com. n/d pre n/d n/d n/d n/d 01234567 8 b / c addr. don't care cas latency = 6 rdqs dq cas latency = 5 rdqs dq d3 d2 d1 d0 d3 d2 d1 d0 t rp b / c: bank / column address rd: read dx: data from b / c com.: command addr.: address b / c pre: precharge dqs : terminations off rdqs : not driven n/d: nop or deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 58 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.9 data termination disable (dterdis) figure 38 data termination disable command the data termination disable command is detected by the device by snooping the bus for read commands when cs is high. the terminators are disabled starting at cl - 1 clocks after the dterdis command is detected and the duration is 4 clocks. the command and address terminators are always enabled. dterdis may only be applied to the gddr3 graphics memory if it is not in the power down or in the self refresh state. the timing relationship between dterdis and other commands is defined by the constraint to avoid contention on the rdqs bus (i.e read to dterdis transistion) or the necessity to have a defined termination on the data bus during write (i.e. write to dterdis transition). act and pre/preall may be applied at any time before or after a dterdis command. figure 39 dternis timing clk# clk ras# cke cas# we# a2-a7, a9 ba0-ba1 don't care a0, a1 a10-a11 a8 ap: autoprecharge cs# clk# clk dtd n/d n/d com . n/d n/d n/d n/d n/d 01234567 8 addr. cas latency = 5 don't care dtd: dterdis com.: command addr.: address b / c 9 n/d n/d data terminations are disabled dq termination n/d : nop or deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 59 rev. 1.52, 06-2004 05142004-zttv-e1oq figure 40 dternis followed by dternis 1. at least 1nop is required between 2 dterdis commands. this correspond to a read to read transistion on the other memory in a 2 rank system. 2. cas latency 5 is used as an example. 3. the dq terminations are switched off (cl-1) clock periods after the dterdis command for a duration of (bl/2 + 2 ) clocks 4. the dashed lines (rdqs bus) describe the rdqs behavior in the case where the dterdis command corresponds to a read command applied to the second graphics dram in a 2 rank system. in this case, rdqs would be driven by the second graphics dram. clk# clk com. n/d n/d n/d n/d n/d 01234567 8 addr. 9 cas latency = 5 10 n/d n/d n/d n/d 11 12 n/d rdqs dq n/d com. n/d n/d n/d n/d addr. cas latency = 5 n/d n/d n/d n/d n/d rdqs dq dtd n/d n/d n/d 13 dtd dtd dtd n/d com. n/d n/d n/d n/d addr. cas latency = 5 n/d n/d n/d n/d n/d rdqs dq dtd n/d n/d dtd n/d don't care b / cx: bank / column address x rd: read n/d : nop or deselect com.: command addr.: address b / c dqs : terminations off rdqs : not driven dtd: dterdis dx#: data from b / cx
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 60 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.9.1 dterdis followed by read figure 41 dterdis command followed by read 1. at least 3 nops are required between a dterdis command and a read command in order to avoid contention on the rdqs bus in a 2 rank system. 2. cas latency 5 is used as an example. 3. the dq terminations are switched off (cl-1) clock periods after the dterdis command for a duration of 4 clocks. clk# clk n/d com. n/d n/d n/d n/d n/d 01234567 8 addr. 9 cas latency = 5 10 n/d n/d don't care b / cx: bank / column address x rd: read dx#: data from b / cx com.: command addr.: address b / c dqs : terminations off rdqs : not driven n/d n/d 11 12 n/d rdqs dq n/d com. n/d n/d n/d n/d addr. cas latency = 5 n/d n/d n/d n/d n/d rdqs dq dtd n/d n/d n/d 13 dtd: dterdis dx0 dx1 dx2 dx3 rd dtd rd dx0 dx1 dx2 dx3 b/cx b/cx n/d: nop or deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 61 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.9.2 dterdis followed by write figure 42 dterdis command followed by write 1. write shown with nominal value of t dqss 2. wdqs can only transition when data is applied at the chip input and during pre- and postambles 3. the minimum distance between dterdis and write is (cl -wl + 4) clocks. clk# clk com. 01234567 8 addr. 9 10 don't care 11 des des des des des des des des des des des des cas latency = 5 write latency = 3 wdqs dq cas latency = 6 write latency = 4 wdqs dq des wr b/cw d3w d2w d1w d0w des b/cw wr com.: command addr.: address b / c dxw: write data from b / c b / cw: bank / column address for write wr: write dqs : terminations off dtd dtd d2w d1w d0w dtd: dterdis des des des des des des des: deselect
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 62 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.10 precharge (pre/preall) figure 43 precharge command the precharge command is used to deactivate the open row in a particular bank (pre) or the open rows in all banks (preall). the bank(s) will enter the idle state and be available again for a new row access after the time t rp . a8/ap sampled with the pre command determines whether one or all banks are to be precharged. for pre commands ba0 and ba1 select the bank. for preall inputs ba0 and ba1 are ?don?t care?. the pre/preall command may not be given unless the t ras requirement is met for the selected bank (pre), or for all banks (preall). clk# clk ras# cke cas# we# a0-7,9-11 ba0-ba1 ba ba: bank address don't care a8 all all: high selects all banks / cs# low selects bank ba table 26 ba1, ba0 precharge bank selection a8 / ap ba1 ba0 precharged bank(s) 0 0 0 bank 0 only 0 0 1 bank 1 only 0 1 0 bank 2 only 0 1 1 bank 3 only 1 x x all banks
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 63 rev. 1.52, 06-2004 05142004-zttv-e1oq figure 44 precharge timing table 27 precharge timing parameters for ?2.0, ?2.2 and ?2.5 speed sorts parameter symbol limit values unit notes - 2.0 - 2.2 - 2.5 min max min max min max row precharge time t rp 13.2 ? 13.2 ? 15.0 ? ns clk# clk act pre nop act nop row row b.x b.x b.x t ras t rp command a0 - a11 ba0, ba1 nop t rc row: row address don't care b.x: bank x act: activate pre: precharge
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 64 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.11 auto refresh command (aref) figure 45 auto refresh command aref is used to do a refresh cycle on one row in each bank. the addresses are generated by an internal refresh controller; external address pins are ?don?t care?. all banks must be idle before the aref command can be applied. the delay between the aref command and the next act or subsequent aref must be at least t rfc (min). the refresh period starts when the aref command is entered and ends t rfc later at which time all banks will be in the idle state. within a period of t ref =32ms the whole memory has to be refreshed. the average periodic interval time from aref to aref is then t refi (max)=7.8s. to improve efficiency bursts of aref commands can be used. such bursts may consist of maximum 8 aref commands. t rfc (min) is the minimum required time between two aref commands inside one aref burst. according to the number of aref commands in one burst the average required time from one aref burst to the next can be increased. example: if the aref bursts consists of 4 aref commands, the average time from one aref burst to the next is 4 * 7.8s = 31.2s. the aref command generates an update of the ocd output impedance and of the addresses, commands and dq terminations. the timing parameter tko ( see section 2.3.2 ) must be complied with. figure 46 auto refresh cycle clk# clk ras# cke cas# we# a0-a11 ba0-ba1 ba: bank address don't care cs# table 28 autorefresh timing parameters for ?2.0, ?2.2 and ?2.5 speed sorts parameter symbol limit values unit notes - 2.0 - 2.2 - 2.5 min max min max min max refresh period (4096 cycles) t ref ?32?32?32ms average periodic auto refresh interval trefi 7.8 7.8 7.8 s delay from aref to next act/ aref t rfc 54?54?54?ns clk# clk arf nop t rp t rfc command pre cke nop nop a.c. arf t refi don't care arf: auto refresh a.c.: aref or act command
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 65 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.12 self-refresh 3.12.1 self-refresh entry (srefen) figure 47 self refresh entry command the self-refresh mode can be used to retain data in the gddr3 graphics ram even if the rest of the system is powered down. when in the self-refresh mode, the gddr3 graphics ram retains data without external clocking. the self-refresh command is initiated like an auto-refresh command except cke is disabled (low). self refresh entry is only possible if all banks are precharged and t rp is met. the gddr3 graphics ram has a build-in timer to accomodate self-refresh operation. the self-refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. once the command is registered, cke must be held low to keep the device in self-refresh mode. when the gddr3 graphics ram has entered the self- refresh mode, all external control signals, except cke are disabled. the address, command and data terminators remain on. the dll and the clock are internally disabled to save power. the user may halt the external clock while the device is in self-refresh mode the next clock after self-refresh entry, however the clock must be restarted before the device can exit self- refresh operation. figure 48 self refresh entry clk# clk ras# cke cas# we# a0-a7 ba0-ba1 don't care a9-a11 a8 cs# clk# clk don't care command cke pa.: precharge all command (or last of pres to each bank) srf: self refresh command t rp pa srf clk/clk# may be halted 1 clock
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 66 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.12.2 self-refresh exit (srefex) figure 49 self refresh exit command to exit the self refresh mode, a stable external clock is needed before setting cke high asynchronously. once the self-refresh exit command is registered, a delay equal or longer than txsc (minimum 200 clock cycles) must be satisfied before any command can be applied. during this time, the dll is automatically enabled, reset and calibrated. cke must remain high for the entire self-refresh exit period and commands must be gated off with cs held high. alternately, nop commands may be registered on each positive clock edge during the self refresh exit interval. figure 50 self refresh exit clk# clk ras# cke cas# we# a0-a11 don't care a9-a11 cs# table 29 self refresh exit timing parameter for ?2.0, ?2.2 and ?2.5 speed sorts parameter symbol limit values units notes - 2.0 - 2.2 - 2.5 min max min max min max self refresh exit time t xsc 200 ? 200 ? 200 ? t ck clk# clk don't care n / d t xsc command cke a.c. a.c.: any command n / d: nop or desel command n / d n / d clk, clk# must be stable
hyb18t256321f?[20/22/25] ddr sgram functional description data sheet 67 rev. 1.52, 06-2004 05142004-zttv-e1oq 3.13 power-down figure 51 power down command unlike sdr sdrams, the gddr3 graphics ram requires cke to be active at all times an access is in progress : from the issuing of a read or write command until completion of the burst. for reads, a burst completion is defined after the rising edge of the read postamble. for writes, a burst completion is defined one clock after the rising edge of the write postamble. for read with autoprecharge and write with autoprecharge, the internal autoprecharge must be completed before entering power-down. power-down is entered when cke is registered low (no access can be in progress). if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding clk, clk and cke. for maximum power saving, the user has the option of disabling the dll prior to entering power-down. in that case the dll must be enabled and reset after exiting power-down, and 200 cycles must occur before a read command can be issued. in power-down mode, cke low and a stable clock signal must be maintained at the inputs of the gddr3 graphics ram, all the other input signals are ?don?t care?. power down duration is limited by the refresh requirements of the device. the power-down state is synchronously exited when cke is registered high (along with a nop or desel command). a valid executable command may be applied txpn later. figure 52 power-down mode clk# clk ra s# cke ca s# we# ba0-ba1 don' t car e a0-a11 cs# 1 2 1: desel, 2: nop table 30 power down exit timing parameter for ?2.0, ?2.2 and ?2.5 speed sorts parameter symbol limit values unit notes - 2.0 - 2.2 - 2.5 min max min max min max precharge power-down exit timing t xpn 4?4?4? t ck clk# clk n / d: nop or deselect command don't care a.c. t xpn (precharge) comm. n / d cke a.c.: any command a.c. power-down mode entry power-down mode exit t is n / d n / d n / d t xard (active)
hyb18t256321f?[20/22/25] ddr sgram electrical characteristics data sheet 68 rev. 1.52, 06-2004 05142004-zttv-e1oq 4 electrical characteristics 4.1 absolute maximum ratings stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage of the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 31 absolute maximum ratings parameter symbol rating unit min. max. power supply voltage v dd -0.5 2.5 v power supply voltage for output buffer v ddq -0.5 2.5 v input voltage v in -0.5 v ddq +0.5 v output voltage v out -0.5 v ddq +0.5 v storage temperature t stg -55 +150 c short circuit output current i out ?50ma table 32 operation conditions parameter symbol range unit min. max. operation temperature (junction) t j 0+90 c operation temperature (case) t c 0+85 c power dissipation p d ?3.2w
hyb18t256321f?[20/22/25] ddr sgram electrical characteristics data sheet 69 rev. 1.52, 06-2004 05142004-zttv-e1oq 4.2 recommended power & dc operation conditions. all values are recommended operating conditions unless otherwise noted. t c = 0 to 85 c. (0c t c +85c, v dd = +2.0 v 0.10 v, v ddq = +2.0 v 0.10 v, see table 1 ) table 33 power & dc operation conditions parameter symbol speed sort limit values unit notes min. typ. max. power supply voltage v dd ?2.0 1.9 2.0 2.1 v 1) 1) v ddq tracks with v dd . ac parameters are measured with v dd and v ddq tied together. ?2.2 1.9 2.0 2.1 v 1) ?2.5 1.9 2.0 2.1 v 1) power supply voltage for i/o buffer v ddq ?2.0 1.9 2.0 2.1 v 1) ?2.2 1.9 2.0 2.1 v 1) ?2.5 1.9 2.0 2.1 v 1) reference voltage v ref ?2.0 0.72* v ddq 0.73* v ddq 0.74* v ddq v 2) 2) v ref is allowed 19mv for dc error and an additionnal 28mv for ac noise. ?2.2 0.72* v ddq 0.73* v ddq 0.74* v ddq 2)3) 3) v ref is expected to equal 73% of v ddq for the transmitting device and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed 2% v ref (dc). thus, from 73% of v ddq. ?2.5 0.72* v ddq 0.73* v ddq 0.74* v ddq 2)3) output low voltage v ol(dc) 0.4* v ddq v input leakage current i il ?5 +5 a 4) 4) i il and i ol are measured with odt disabled. clk input leakage current i ilc ?5 +5 a output leakage current i ol ?5 +5 a 4)
hyb18t256321f?[20/22/25] ddr sgram electrical characteristics data sheet 70 rev. 1.52, 06-2004 05142004-zttv-e1oq 4.3 dc & ac logic input levels. (0c t c +85c, v dd = +2.0 v 0.10 v, v ddq = +2.0 v 0.10 v, see table 1 ) 1. the dc values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a valid level. 2. input slew rate = 2 v/ns. if the input slew rate is less than 2 v/ns, input timing may be compromised. all slew rates are measured between v il(dc) and v ih(dc) . 3. v ih overshoot : v ih(max) = v ddq +0.5 v for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. v il undershoot: v il(min) = 0 v for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. 4.4 differential cloc k dc and ac levels (0c t c +85c, v dd = +2.0 v 0.10 v, v ddq = +2.0 v 0.10 v, see table 1 ) 1. all voltages referenced to v ss 2. v id is the magnitude of the difference between the input level on clk and the input level on clk . 3. the value of v ix is expected to equal 0.7 x v ddq of the transmitting device and must track variations in the dc level of the same. table 34 dc & ac logic input levels parameter symbol limit values unit notes min. max. input logic high voltage, dc v ih(dc) 0.7 * v ddq + 0.15 ? v 1 input logic low voltage, dc v il(dc) ?0.7 * v ddq -0.15 v 1 input logic high voltage, ac v ih (ac) 0.7 * v ddq +0.4 ? v 2,3 input logic low voltage, ac v il(ac) ?0.7 * v ddq - 0.4 v 2,3 input logic high, dc, reset pin v ihr(dc) 0.8 * v ddq v ddq + 0.3 v input logoc low, dc, reset pin v ilr(dc) -0.3 0.2 * v ddq v table 35 differential clock dc and ac input conditions parameter symbol limit values unit note s min. max. clock input mid-point voltage, clk and clk v mp(dc) v ref - 0.1 v ref + 0.1 v 1 clock input voltage level, clk and clk v in(dc) 0.42 v ddq + 0.3 v 1 clock dc input differential voltage, clk and clk v id(dc) 0.3 v ddq v1 clock ac input differential voltage, clk and clk v id(ac) 0.5 v ddq + 0.5 v 1, 2 ac differential crossing point input voltage v ix(ac) v ref - 0.15 v ref + 0.15 v 1, 3
hyb18t256321f?[20/22/25] ddr sgram electrical characteristics data sheet 71 rev. 1.52, 06-2004 05142004-zttv-e1oq 4.5 output test conditions figure 53 output test circuit note: v ddq =2.0 0.1 v, tc=0 c to 85 c, see table 1 4.6 pin capacitances 1. the input capcitance per pin group will not differ by more than this maximum amount for any given device. 2. the io capacitance per rdqs and dq byte / group will not differ by more than this maximum amount for any given device. table 36 capacitances parameter symbol min max unit notes input capacitance: clk, clk cck 2.0 4.0 pf input capacitance delta: clk, clk cdck 0.1 pf 1 input capacitance: a0-a11, ba0-1,cke, cs , cas , ras , we , cke, res ci 2.0 4.0 pf input capacitance delta: a0-a11, ba0-1,cke, cs , cas , ras , we , cke, res dci 0.6 pf 1 input capacitance: dq0-dq31, rdqs0-rdqs3 , wdqs0-wdqs3, dm0- dm3 cio 2.5 4.5 pf input capacitance delta: dq0-dq31, rdqs0-rdqs3 , wdqs0-wdqs3, dm0- dm3 dcio 0.6 pf 2 dq 60 ohm test point dqs v ddq
hyb18t256321f?[20/22/25] ddr sgram electrical characteristics data sheet 72 rev. 1.52, 06-2004 05142004-zttv-e1oq 4.7 driver current characteristics 4.7.1 driver iv characteristics at 40 ohms figure 54 represents the driver pull-down and pull-up iv characteristics under process, voltage and temperature best and worst case conditions. the actual driver pull-down and pull-up current must lie between these two bounding curves. the value of the external zq resistor is 240 ?, setting the nominal driver output impedance to 40 ? . figure 54 40 ohm driver pull-down and pull-up characteristics table 37 lists the numerical values of the minimum and maximum allowed values of the output driver pull-down and pull-up iv characteristics. table 37 programmed driver iv characteristics at 40 ohm voltage (v) pull-down current (ma) pull-up current (ma) minimum maximum minimum maximum 0.1 2.32 3.04 -2.44 -3.27 0.2 4.56 5.98 -4.79 -6.42 0.3 6.69 8.82 -7.03 -9.45 0.4 8.74 11.56 -9.18 -12.37 0.5 10.70 14.19 -11.23 -15.17 0.6 12.56 16.72 -13.17 -17.83 0.7 14.34 19.14 -15.01 -20.37 0.8 16.01 21.44 -16.74 -22.78 0.9 17.61 23.61 -18.37 -25.04 1.0 19.11 26.10 -19.90 -27.17 1.1 20.53 28.45 .21.34 -29.17 1.2 21.92 30.45 -22.72 -31.25 1.3 23.29 32.73 -24.07 -33.00 1.4 24.65 34.95 -25.40 -35.00 1.5 26.00 37.10 -26.73 -37.00 1.6 27.35 39.15 -28.06 -39.14 1.7 28.70 41.01 -29.37 -41.25 1.8 - 42.53 - -43.29 1.9 - 43.71 - -45.23 pull-down characterstics 0 5 10 15 20 25 30 35 40 45 50 0.0 0.5 1.0 1.5 2.0 vout (v) iout (ma) pull-up characterstics -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0.00.51.01.52.0 vddq - vout (v) iout (ma)
hyb18t256321f?[20/22/25] ddr sgram electrical characteristics data sheet 73 rev. 1.52, 06-2004 05142004-zttv-e1oq 4.8 termination iv characteristic at 60 ohms figure 55 represents the dq termination pull-up iv characteristic under process, voltage and temperature best and worst case conditions. the actual dq termination pull-up current must lie between these two bounding curves. the value of the external zq resistor is 240 ?, setting the nominal dq termination impedance to 60 ? . (extended mode register programmed to zq/4). figure 55 60 ohm active termination characteristic table 38 lists the numerical values of the minimum and maximum allowed values of the output driver termination iv characteristic. table 38 programmed terminator characterisitc at 60 ohm voltage (v) terminator pull-up current (ma) voltage (v) terminator pull-up current (ma) minimum maximum minimum maximum 1.0 -13.27 -18.11 0.1 -1.63 -2.18 1.1 -14.23 -19.45 0.2 -3.19 -4.28 1.2 -15.14 -20.83 0.3 -4.69 -6.30 1.3 -16.04 -22.00 0.4 -6.12 -8.25 1.4 -16.94 -23.33 0.5 -7.49 -10.11 1.5 -17.82 -24.67 0.6 -8.78 -11.89 1.6 -18.70 -26.09 0.7 -10.01 -13.58 1.7 -19.58 -27.50 0.8 -11.16 -15.19 1.8 - -28.86 0.9 -12.25 -16.69 1.9 - -30.15 60 ohm termination characterstics -35 -30 -25 -20 -15 -10 -5 0 0.00.51.01.52.0 vddq - vout (v) iout (ma)
hyb18t256321f?[20/22/25] ddr sgram electrical characteristics data sheet 74 rev. 1.52, 06-2004 05142004-zttv-e1oq 4.9 termination iv characteristic at 120 ohms figure 56 represents the dq or add/cmd termination pull-up iv characteristic under process, voltage and temperature best and worst case conditions. the actual termination pull-up current must lie between these two bounding curves. the value of the external zq resistor is 240 ?, setting the nominal termination impedance to 120 ? . (extended mode register programmed to zq/2 for dq terminations or cke = 0 at the res transition during power-up for add/cmd terminations). figure 56 120 ohm active termination characteristic table 39 lists the numerical values of the minimum and maximum allowed values of the termination iv characteristic. table 39 programmed terminator characterisitics at 120 ohm voltage(v) terminator pull-up current (ma) voltage (v) terminator pull-up current (ma) minimum maximum minimum maximum 1.0 -6.63 -9.06 0.1 -0.81 -1.09 1.1 -7.11 -9.72 0.2 -1.60 -2.14 1.2 -7.57 -10.42 0.3 -2.34 -3.15 1.3 -8.02 -11.00 0.4 -3.06 -4.12 1.4 -8.47 -11.67 0.5 -3.74 -5.06 1.5 -8.91 -12.33 0.6 -4.39 -5.94 1.6 -9.35 -13.05 0.7 -5.00 -6.79 1.7 -9.79 -13.75 0.8 -5.58 -7.59 1.8 - -14.43 0.9 -6.12 -8.35 1.9 - -15.08 120 ohm termination characterstics -16 -14 -12 -10 -8 -6 -4 -2 0 0.0 0.5 1.0 1.5 2.0 vddq - vout (v) iout (ma)
hyb18t256321f?[20/22/25] ddr sgram electrical characteristics data sheet 75 rev. 1.52, 06-2004 05142004-zttv-e1oq 4.10 termination iv characteristic at 240 ohms figure 57 represents the add/cmd termination pull-up iv characteristic under process, voltage and temperature best and worst case conditions. the actual add/cmd termination pull-up current must lie between these two bounding curves. the value of the external zq resistor is 240 ?, setting the nominal termination impedance to 240 ? . (cke = 1at the res transition during power-up for add/cmd terminations). figure 57 240 ohm active termination characteristic table 40 lists the numerical values of the minimum and maximum allowed values of the add/cmd termination iv characteristic. table 40 programmed terminator characterisitc at 240 ohm voltage (v) terminator pull-up current (ma) voltage (v) terminator pull-up current (ma) minimum maximum minimum maximum 1.0 -3.32 -4.53 0.1 -0.41 -0.55 1.1 -3.56 -4.86 0.2 -0.80 -1.07 1.2 -3.79 -5.21 0.3 -1.17 -1.58 1.3 -4.01 -5.50 0.4 -1.53 -2.06 1.4 -4.23 -5.83 0.5 -1.87 -2.53 1.5 -4.46 -6.17 0.6 -2.20 -2.97 1.6 -4.68 -6.52 0.7 -2.50 -3.40 1.7 -4.90 -6.88 0.8 -2.79 -3.80 1.8 - -7.21 0.9 -3.06 -4.17 1.9 - -7.54 240 ohm termination characterstics -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 0.00.51.01.52.0 vddq - vout (v) iout (ma)
hyb18t256321f?[20/22/25] ddr sgram electrical characteristics data sheet 76 rev. 1.52, 06-2004 05142004-zttv-e1oq 4.11 operating currents 4.11.1 operating current ratings (0c t c +85c, v dd = +2.0 v 0.10 v, v ddq = +2.0 v 0.10 v, see table 1 ) 4.12 operating current measurement conditions (0c t c +85c, v dd = +2.0v 0.10 v, v ddq = +2.0 v 0.10 v, see table 1 ) table 41 operating current ratings parameter symbol limit values unit notes - 2.0 - 2.2 - 2.5 typ. typ. typ. operating current i dd0 238 222 204 ma 1)2)3) 1) i dd specifications are tested after the device is properly initialized. 2) input slew rate = 2 v/ns. 3) mesured with output open and on die termination off. operating current i dd1 258 241 222 ma 1)2)3) precharge power-down standby current i dd2p 86 81 75 ma 1)2)3) precharge floating standby current i dd2f 136 127 118 ma 1)2)3) precharge quiet standby current i dd2q 98 92 86 ma 1)2)3) active power-down standy current i dd3p 86 81 75 ma 1)2)3) active standby current i dd3n 158 148 138 ma 1)2)3) operating current burst read i dd4r 412 385 355 ma 1)2)3) operating current burst write i dd4w 278 265 245 ma 1)2)3) auto-refresh current ( t rc =min( t rfc )) i dd5b 374 348 312 ma 1)2)3) auto-refresh current at t refi i dd5d 88 83 77 ma 1)2)3) self refresh current i dd6 555ma 1)2)3)4) 4) enables on-chip refresh and address counter. operating current i dd7 548 509 460 ma 1)2)3) table 42 operating current measurement conditions symbol parameter/condition i dd0 operating current - one bank, activate - precharge t ck =min( t ck ), t rc =min( t rc ) databus inputs are switching; address and control inputs are switching, cs = high between valid commands. i dd1 operating current - one bank, activate - read - precharge one bank is accessed with t ck =min( t ck ), t rc =min( t rc ), cl = cl(min), address and control inputs are switching; cs = high between valid commands. i out =0ma i dd2p precharge power-down standby current all banks idle, power-down mode, cke is low, t ck =min( t ck ), data bus inputs are stable. i dd2f precharge floating standby current all banks idle; cs is low, cke is high, t ck =min( t ck ); address and control inputs are switching; data bus input are stable.
hyb18t256321f?[20/22/25] ddr sgram electrical characteristics data sheet 77 rev. 1.52, 06-2004 05142004-zttv-e1oq 1. data bus consists of dq, dm, wdqs 2. definitions for idd : low is defined as vin = 0.4 x v ddq ; high is defined as v in = v ddq ; stable is defined as inputs are stable at a high level. switching is defined as inputs are changing between high and low every clock cycle for address and control signals, and inputs changing 50% of each data transfer for dq signals. 3. legend : a=activate, ra=read with autoprecharge, d=deselect i dd2q precharge quiet standby current cs is high, all banks idle, cke is high, t ck =min( t ck ), address and other control inputs stable, data bus inputs are stable. i dd3p active power-down standby current all banks active, cke is low, address and control inputs are stable; data bus inputs are stable; standard active power-down mode. i dd3n active standby current all banks active, cs is high, cke is high, t rc =max( t ras ), t ck =min( t ck ); address and control inputs are switching; data bus inputs are switching; i out = 0 ma. i dd4r operating current - burst read all banks active; continuous read bursts, cl = cl(min); t ck=min( t ck ); address and control inputs are switching; data bus inputs are switching. i dd4w operating current - burst write all banks active; continuous write bursts; t ck =min( t ck ); address and control inputs are switching; data bus inputs are switching. i dd5b burst auto refresh current refresh command at t rc =min( t rfc ); t ck =min( t ck ); cke is high, cs is high between all valid commands; other command and address inputs are switching; data bus inputs are switching. i dd5d distributed auto refresh current tck=tckmin; refresh command every trefi; cke is high, cs is high between valid commands; other command and address inputs are switching; data bus inputs are switching. i dd6 self refresh current cke max( v il ), external clock off, ck and ck low; address and control inputs are stable; data bus inputs are stable. i dd7 operating bank interleave read current 1. all banks interleaving with cl = cl(min); trcd = trcdrd(min); trrd = trrd(min); iout=0ma; address and control inputs are stable during deselect; data bus inputs are switching. 2: timing pattern: -2.5 (400 mhz, cl=6) : t ck = 2.5ns, t rcdrd = 7. t ck ; trrd = 4. t ck ; t rc = 18. t ck read: a0 ra3 d d a1 d d ra0 a2 d d ra1 a3 d d ra2 d d -2.2 (455 mhz, cl6) : t ck = 2.2ns, t rcdrd = 7. t ck ; trrd = 4. t ck ; t rc = 18. t ck read: a0 ra3 d d a1 d d ra0 a2 d d ra1 a3 d d ra2 d d -2.0 (500 mhz, cl6) : t ck = 2.0ns, t rcdrd = 7. t ck ; trrd = 4. t ck ; t rc = 18. t ck read: a0 ra3 d d a1 d d ra0 a2 d d ra1 a3 d d ra2 d d table 42 operating current measurement conditions symbol parameter/condition
hyb18t256321f?[20/22/25] ddr sgram electrical characteristics data sheet 78 rev. 1.52, 06-2004 05142004-zttv-e1oq 4.13 summary of timing parameters for ?2.0 ns, ?2.2 ns and ?2.5 ns speed sorts in dll on mode table 43 timing parameters for ?2.0, ?2.2 and ?2.5 speed sorts parameter read latency sym- bol limit values unit notes - 2.0 - 2.2 - 2.5 min max min max min max clock and clock enable clock cycle time 7 t ck7 2.0 4.0 2.2 4.0 2.5 4.0 ns 6 t ck6 2.0 4.0 2.2 4.0 2.5 4.0 ns 5 t ck5 ? ? 2.7 4.0 3.0 4.0 ns system frequency 7 f ck7 250 500 250 455 250 400 mhz 6 f ck6 250 500 250 455 250 400 mhz 5 f ck5 ? ? 250 370 250 333 mhz clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck minimum clock half period t hp 0.45 ? 0.45 ? 0.45 ? t ck 1 command and address setup and hold timing address/command input setup time t is 0.75 ? 0.75 ? 0.85 ? ns address/command input hold time t ih 0.75 ? 0.75 ? 0.85 ? ns address/command input pulse width t ipw 0.85 ? 0.85 ? 0.85 ? t ck mode register set timing mode register set cycle time t mrd 4? 4? 4? t ck mode register set to read timing t mrdr 12 ? 12 ? 12 ? t ck row timing row cycle time t rc 37.2 ? 39.6 ? 45.0 ? ns row active time t ras 24.0 8 x t refi 26.2 8 x t refi 30.0 8 x t refi ns act(a) to act(b) command period t rrd 8.0 ? 8.8 ? 10.0 ? ns row precharge time t rp 13.2 ? 13.2 ? 15.0 ? ns row to column delay time for reads t rcdrd 16.0 ? 17.5 ? 17.5 ? ns row to column delay time for writes t rcdwr t rcdwr(min) = t rcdrd(min) - (wl + 1) x t ck(min) ns column timing cas(a) to cas(b) command period t ccd 2? 2? 2? t ck 2 write to read command delay t wtr 6.0 ? 6.6 ? 7.5 ? ns 3 read to write command delay t rtw t rtw (min)= (cl+4-wl) t ck 4 write cycle timing parameters for data and data strobe write command to first wdqs latching transition t dqss wl - 0.25 wl +0.25 wl - 0.25 wl +0.25 wl - 0.25 wl +0.25 t ck data-in and data mask to wdqs setup time t ds 0.375 ? 0.375 ? 0.425 ? ns
hyb18t256321f?[20/22/25] ddr sgram electrical characteristics data sheet 79 rev. 1.52, 06-2004 05142004-zttv-e1oq 1. t hp is the lesser of t cl minimum and t ch minimum actually applied to the device clk, clk inputs 2. t ccd is either for gapless consecutive reads or gapless consecutive writes. 3. t wtr and t wr start at the first rising edge of clk after the last valid (falling) wdqs edge of the slowest wdqs signal . 4. please round up t rtw to the next integer of t ck . data-in and data mask to wdqs hold time t dh 0.375 ? 0.375 ? 0.425 ? ns data-in and dm input pulse width (each input) t dipw 0.45 ? 0.45 ? 0.45 ? t ck dqs input low pulse width t dqsl 0.45 ? 0.45 ? 0.45 ? t ck dqs input high pulse width t dqsh 0.45 ? 0.45 ? 0.45 ? t ck dqs write preamble time t wpre 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs write postamble time t wpst 0.75 1.25 0.75 1.25 0.75 1.25 t ck write recovery time t wr 11.0 ? 11.0 ? 12.5 ? ns 3 read cycle timing parameters for data and data strobe data access time from clock t ac ?0.4 0.4 ?0.45 0.45 ?0.5 0.5 ns read preamble t rpre 0.75 1.25 0.75 1.25 0.75 1.25 t ck read postamble t rpst 0.75 1.25 0.75 1.25 0.75 1.25 t ck data-out high impedance time from clk t hz t ac min t ac max t ac min t ac max t ac min t ac max ns data-out low impedance time from clk t lz t ac min t ac max t ac min t ac max t ac min t ac max ns dqs edge to clock edge skew t dqsck -0.4 +0.4 -0.45 +0.45 -0.5 +0.5 ns dqs edge to output data edge skew t dqsq ?0.225?0.25?0.28ns data hold skew factor t qhs 00.22500.25000.280ns data output hold time from dqs t qh t hp ? t qhs t hp ? t qhs t hp ? t qhs ns refresh/power down timing refresh period (4096 cycles) t ref ?32 ?32 ?32 ms average periodic auto refresh interval t refi 7.8 7.8 7.8 s delay from aref to next act/ aref t rfc 54 ? 54 ? 54 ? ns self refresh exit time t xsc 200 ? 200 ? 200 ? t ck precharge power down exit time t xpn 4? 4? 4? t ck active power down exit time t xard 6? 6? 6? t ck other timing parameters res to cke setup timing t ats 10 ? 10 ? 10 ? ns res to cke hold timing t ath 10 ? 10 ? 10 ? ns termination update keep out timing t ko 10 ? 10 ? 10 ? ns rev. id emrs to dq on timing t ridon ?20 ?20 ?20 ns rev. id emrs to dq off timing t ridoff ?20 ?20 ?20 ns table 43 timing parameters for ?2.0, ?2.2 and ?2.5 speed sorts parameter read latency sym- bol limit values unit notes - 2.0 - 2.2 - 2.5 min max min max min max
hyb18t256321f?[20/22/25] ddr sgram electrical characteristics data sheet 80 rev. 1.52, 06-2004 05142004-zttv-e1oq 4.14 ac characteristics and settings the following tables are meant as a guideline to correctly set the most important timing parameters depending on speed sort and clock frequency. table 44 hyb18t256321f?20 frequency / t ck cas latency t rc t rfc t ras t rp t wr t rrd t rcdrd t rcdwr unit 500 mhz / 2.0ns 7,6 19 27 12 7 6 4 8 5 t ck 455 mhz / 2.2ns 7,6 17 25 11 6 5 4 8 5 t ck 400 mhz / 2.5ns 5 16 22 10 6 5 4 7 4 t ck 370 mhz / 2.7ns 5 14 20 9 5 5 3 6 4 t ck 300 mhz / 3.0ns 5 13 18 8 5 4 3 6 4 t ck 266 mhz / 3.8ns 5 11 15 7 4 3 3 5 3 t ck 250mhz / 4.0ns 5 10 14 6 4 3 2 4 3 t ck table 45 hyb18t256321f?22 frequency / t ck cas latency t rc t rfc t ras t rp t wr t rrd t rcdrd t rcdwr unit 455 mhz / 2.2ns 7,6 18 25 12 6 5 4 8 5 t ck 400 mhz / 2.5ns 7,6 17 22 11 6 5 4 7 5 t ck 370 mhz / 2.7ns 5 15 20 10 5 5 4 7 5 t ck 300 mhz / 3.0ns 5 14 18 9 5 4 3 6 4 t ck 266 mhz / 3.8ns 5 11 15 7 4 3 3 5 3 t ck 250mhz / 4.0ns 5 11 14 7 4 3 3 5 3 t ck table 46 hyb18t256321f?25 frequency / t ck cas latency t rc t rfc t ras t rp t wr t rrd t rcdrd t rcdwr unit 400 mhz / 2.5ns 7,6 18 22 12 6 5 4 7 5 t ck 370 mhz / 2.7ns 7,6 18 20 12 6 5 4 7 5 t ck 300 mhz / 3.0ns 5 15 18 10 5 5 4 6 4 t ck 266 mhz / 3.8ns 5 12 15 8 4 4 3 5 3 t ck 250mhz / 4.0ns 5 12 14 8 4 4 3 5 3 t ck
hyb18t256321f?[20/22/25] ddr sgram package outlines data sheet 81 rev. 1.52, 06-2004 05142004-zttv-e1oq 5 package outlines figure 58 package outline fbga 1. the package is conforming with jedec mo216 2. the inner matrix of 4x4 balls is reserved for thermal contacts all dimensions in mm. 11.00 0.10 11.00 0.10 ball a1 indicator top view 13 246 579 81012 11 a b c d e f g h j l m k 0.40 0.80 (11x) 0.40 0.80 (11x) balls view 1.20 max 0 . 1 2 c 0 . 1 0 c c
hyb18t256321f?[20/22/25] ddr sgram package outlines data sheet 82 rev. 1.52, 06-2004 05142004-zttv-e1oq 5.1 package thermal characteristics 1. theta_ja : junction to ambient thermal resistance. the values have been obtained by simulation using the conditions stated in the jedec jesd-51 standard. 2. theta_jb : junction to board thermal resistance. the value has been obtained by simulation. 3. theta_jc : junction to case thermal resistance. the value has been obtainned by simulation. table 47 p-fbga 144 package thermal resitances theta_ja theta_jb theta_jc jedec board 1s0p 2s0p air flow 0 m/s 1 m/s 3 m/s 0 m/s 1 m/s 3 m/s - - k/w 48.8 40.2 35.1 27.0 23.5 22.0 6.0 3.9
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